Verilog Coding for Logic Synthesis

Table of Figures

Figure 2.1 Diagram Showing an ASIC Design Flow

Figure 2.2 Diagram Indicating Step 1 of an ASIC Design Flow: Specification

Figure 2.3 Diagram Showing the Definition of Architecture and Micro Architecture

Figure 2.4 Diagram Indicating Step 2 of an ASIC Design Flow: RTL Coding

Figure 2.5 Diagram Indicating Step 3 of an ASIC Design Flow: Testbench and Simulation

Figure 2.6 Diagram Indicating Step 4 of an ASIC Design Flow: Synthesis

Figure 2.7 Diagram Indicating Step 5 of an ASIC Design Flow: Pre Layout Timing Analysis

Figure 2.8 Diagram Indicating Step 6 of an ASIC Design Flow: Auto Place & Route (APR)

Figure 2.9 Diagram Indicating Step 7 of an ASIC Design Flow: Back Annotation

Figure 2.10 Diagram Indicating Step 8 of an ASIC Design Flow: Post Layout Timing Analysis

Figure 2.11 Diagram Indicating Step 9 of an ASIC Design Flow: Logic Verification

Figure 4.1 Diagram Showing Two Sub-modules Connected on a Fullchip Level

Figure 4.2 Diagram Showing a Fullchip Level of Global Clock Interconnect

Figure 4.3 Diagram Showing Ideal Connectivity of Clock Signal in a Design

Figure 4.4 Diagram Showing an Output Flip-flop Driving Another Flip-flop

Figure 4.5 Diagram Showing a Gated Clock Driving a Flip-flop

Figure 4.6 Diagram Showing Signal Gated Driving Clock of 32 Flip-flops

Figure 4.7 Diagram Showing Multiple Gated Signal to Drive 32 Flip-flops

Figure 4.8 Diagram Showing a Design with an Asynchronous Reset Flip-flop

Figure 4.9 Diagram Showing a Design with a Synchronous Reset ...