Verilog Coding for Logic Synthesis

Glossary

APR auto place and route.

ASIC application-specific integrated circuit.

Back annotation back annotating physical layout information from layout to design to enable a more accurate simulation.

Contention more than one signal is driving a node.

Design compiler a synthesis tool from Synopsys.

EDA electronic design automation.

FPGA field programmable gate array.

HDL hardware description language.

Hold time time required for a signal to be held valid with reference to clock change.

Mentor Graphics an EDA tool company.

Parasitics resistance and capacitance that is caused by layout routing.

RTL register transfer level.

Schematic capture a method of design where circuits are hand drawn.

Sensitivity list a list that contains all the signals that will invoke the corresponding process.

Setup time time required for a signal to be held valid prior to a clock change.

Simulation using a set of input stimulus to verify the functionality of a design.

Summit Design an EDA tool company.

Synopsys an EDA tool company.

Synthesis the process of conversion from HDL to logic gates using a synthesis tool.

Synthesizable code HDL code that is coded in a manner that allows it to be synthesized.

Test bench a wraparound on a design that injects stimulus into the “design under test” to verify the functionality of the design.

UDP user-defined primitive.

Verilog an HDL language.

VHDL another HDL language.

VLSI very-large-scale integration.