Verilog Coding for Logic Synthesis

Contents

Table of Figures

Table of Examples

List of Tables

Preface

Acknowledgments

Trademarks

1 Introduction

2 Asic Design Flow

2.1 Specification

2.2 RTL Coding

2.2.1 Types of Verilog Code: RTL, Behavioral, and Structural

2.3 Test Bench and Simulation

2.4 Synthesis

2.5 Prelayout Timing Analysis

2.6 APR

2.7 Back Annotation

2.8 Post layout Timing Analysis

2.9 Logic Verification

3 Verilog Coding

3.1 Introduction to Basic Verilog Concepts

3.1.1 Verilog Syntax

3.1.2 Comments

3.1.3 Numbers

3.1.4 Verilog Data Type

3.1.5 Signal Strength

3.2 Verilog Gate-Level Primitives

3.3 User-Defined Primitives

3.3.1 Combinational UDP

3.3.2 Sequential UDP

3.4 Concurrent and Sequential Statements

4 Coding Style: Best-Known Method for Synthesis

4.1 Naming Convention

4.2 Design Partitioning

4.3 Clock

4.3.1 Internally Generated Clock

4.3.2 Gated Clock

4.4 Reset

4.4.1 Asynchronous Reset

4.4.2 Synchronous Reset

4.5 Timing Loop

4.6 Blocking and Nonblocking Statement

4.7 Sensitivity List

4.8 Verilog Operators

4.8.1 Conditional Operators

4.8.2 Bus Concatenation Operator

4.8.3 Shift Operator

4.8.4 Arithmetic Operator

4.8.5 Division Operator

4.8.6 Modulus Operator

4.8.7 Logical Operator

4.8.8 Bitwise Operator

4.8.9 Equality Operator

4.8.10 Reduction Operator

4.8.11 Relational Operator

4.9 Latch Inference

4.10 Memory Array

4.11 State Machine Design

4.11.1 Intelligent Traffic Control System

5 Design Example of Programmable Timer

5.1 Programmable Timer Design Specification

5.2 Microarchitecture Definition for Programmable ...