Advanced Frequency Synthesis by Phase Lock

APPENDIX P

PHASE DETECTORS

The sample-and-hold (S&H) phase detector (PD) [FS2, pp. 188–197] has been largely replaced by the phase frequency detector (PFD) driving a charge pump (CP) [FS2, pp.197–211]. Historically, the PFD had the advantage of providing an acquisition aid [FS2, pp. 452–459] along with the PD in a single IC, whereas the S&H PD required additional logic circuitry [FS2, pp. 465–472] to perform that function. While this advantage seems to be lacking in a synthesizer IC, the CP PD is nevertheless almost universally used in ICs, for reasons that are not obvious. It may be easier to implement or it may have some performance advantage or, perhaps, design inertia plays a role.

The S&H PD provides a DC output in steady state and transients that can produce reference spurs are due to secondary effects, such as logic signals coupled capacitively or through ground currents. It provides stepped outputs in response to the shaped quantization noise in a Σ∆ synthesizer. This is easier to compensate than are the pulses from a PFD and it is easier to observe the phase with these levels, which is one reason that we have used it in some simulations.

The basic output from a PFD and CP is a pulse, with obvious implications for reference spurs. To avoid spurs, the PFD is normally used in a type-2 loop, so there will be zero phase error and, therefore, zero pulse width at steady state. Unfortunately, the PFD-and-CP tends to have a narrow nonlinear region just at zero phase [FS2, pp. ...