Algorithms and Parallel Computing

18.9 COMPARING THE THREE DESIGNS

The hardware structure for all three types of design above show similarities and differences. All designs have tasks that contain storage registers and have two inputs and two outputs. Designs 1 and 2 contain one register in each task, while design 3 contains three tasks. All the registers in designs 1 and 2 are clocked on the same edge of the clock, while design 3 has the even tasks clocked on the rising edge and the odd tasks clocked on the falling edge.

The click period of design 1 could be the longest since the input to the mux when select = 1 will propagate through m XOR gates in each clock cycle. The architectures of the three designs dictate respective clock periods given by

(18.47)

(18.48)

(18.49)

where τ_setup is the setup time for the registers, τ_D is the register delay, τ_XOR is the XOR gate delay, τ_AND is the AND gate delay, and τ_p is the propagation time for a signal through all the tasks. This last delay component is due to the top signal in design 2, which is merely passed between the tasks perhaps through a long bus. More accurate predictions of system speeds are obtained for actual implementations.