All-Digital Frequency Synthesizer in Deep-Submicron CMOS

CONTENTS

PREFACE

1 INTRODUCTION

1.1 Frequency Synthesis

1.1.1 Noise in Oscillators

1.1.2 Frequency Synthesis Techniques

1.2 Frequency Synthesizer as an Integral Part of an RF Transceiver

1.2.1 Transmitter

1.2.2 Receiver

1.2.3 Toward Direct Transmitter Modulation

1.3 Frequency Synthesizers for Mobile Communications

1.3.1 Integer-N PLL Architecture

1.3.2 Fractional-N PLL Architecture

1.3.3 Toward an All-Digital PLL Approach

1.4 Implementation of an RF Synthesizer

1.4.1 CMOS vs. Traditional RF Process Technologies

1.4.2 Deep-Submicron CMOS

1.4.3 Digitally Intensive Approach

1.4.4 System Integration

1.4.5 System Integration Challenges for Deep-Submicron CMOS

2 DIGITALLY CONTROLLED OSCILLATOR

2.1 Varactor in a Deep-Submicron CMOS Process

2.2 Fully Digital Control of Oscillating Frequency

2.3 LC Tank

2.4 Oscillator Core

2.5 Open-Loop Narrowband Digital-to-Frequency Conversion

2.6 Example Implementation

2.7 Time-Domain Mathematical Model of a DCO

2.8 Summary

3 NORMALIZED DCO

3.1 Oscillator Transfer Function and Gain

3.2 DCO Gain Estimation

3.3 DCO Gain Normalization

3.4 Principle of Synchronously Optimal DCO Tuning Word Retiming

3.5 Time Dithering of DCO Tuning Input

3.5.1 Oscillator Tune Time Dithering Principle

3.5.2 Direct Time Dithering of Tuning Input

3.5.3 Update Clock Dithering Scheme

3.6 Implementation of PVT and Acquisition DCO Bits

3.7 Implementation of Tracking DCO Bits

3.7.1 High-Speed Dithering of Fractional Varactors

3.7.2 Dynamic Element Matching of Varactors

3.7.3 DCO ...