book

Compact Models for Integrated Circuit Design

Name: Compact Models for Integrated Circuit Design
Author: Samar K. Saha
ISBN: 9781351831079

by Samar K. Saha

September 2018

Intermediate to advanced

545 pages

14h 16m

English

CRC Press

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Cover
Half Title
Title Page
Copyright Page
Dedication
Table of Contents
Preface
Author
1. Introduction to Compact Models
1.1 Compact Models for Circuit Simulation1.1.1 Compact Device Models1.1.2 Compact Interconnect Models1.2 Brief History of Compact Device Modeling1.2.1 Early History of Compact MOSFET Modeling1.2.2 Recent History of Compact MOSFET Modeling1.2.2.1 Threshold Voltage–Based Compact MOSFET Modeling1.2.2.2 Surface Potential–Based Compact MOSFET Modeling1.2.2.3 Charge-Based Compact MOSFET Modeling1.3 Motivation for Compact Modeling1.4 Compact Model Usage1.5 Compact Model Standardization1.6 SummaryExercises
2. Review of Basic Device Physics
2.1 Introduction2.2 Semiconductor Physics2.2.1 Energy Band Model2.2.2 Carrier Statistics2.2.3 Intrinsic Semiconductors2.2.3.1 Intrinsic Carrier Concentration2.2.3.2 Effective Mass of Electrons and Holes2.2.4 Extrinsic Semiconductors2.2.4.1 Fermi Level in Extrinsic Semiconductor2.2.4.2 Fermi Level in Degenerately Doped Semiconductor2.2.5 Carrier Transport in Semiconductors2.2.5.1 Carrier Mobility and Drift Current2.2.5.2 Electrical Resistivity2.2.5.3 Sheet Resistance2.2.5.4 Velocity Saturation2.2.5.5 Diffusion of Carriers2.2.5.6 Nonuniformly Doped Semiconductors and Built-In Electric Field2.2.6 Generation–Recombination2.2.6.1 Injection Level2.2.6.2 Recombination Processes2.2.7 Basic Semiconductor Equations2.2.7.1 Poisson’s Equation2.2.7.2 Carrier Concentration in Terms of Electrostatic Potential2.2.7.3 Quasi-Fermi Level2.2.7.4 Transport Equations2.2.7.5 Continuity Equations2.3 Theory of n-Type and p-Type Semiconductors in Contact2.3.1 Basic Features of pn-Junctions2.3.2 Built-In Potential2.3.3 Step Junctions2.3.3.1 Junction Potential and Electric Field2.3.4 pn-Junctions under External Bias2.3.4.1 One-Sided Step Junctions2.3.5 pn-Junction Equations2.3.5.1 Relationship between Minority Carrier Density and Junction Voltage2.3.6 pn-Junctions I–V Characteristics2.3.6.1 Temperature Dependence of pn-Junction Leakage Current2.3.6.2 Limitations of pn-Junction Current Equation2.3.6.3 Bulk Resistance2.3.6.4 Junction Breakdown Voltage2.3.7 pn-Junction Dynamic Behavior2.3.7.1 Junction Capacitance2.3.7.2 Diffusion Capacitance2.3.7.3 Small Signal Conductance2.3.8 Diode Equivalent Circuit for Circuit CAD2.4 SummaryExercises

3. Metal-Oxide-Semiconductor System
3.1 Introduction3.2 MOS Capacitor at Equilibrium3.2.1 Work Function3.2.2 Oxide Charges3.2.2.1 Interface-Trapped Charge3.2.2.2 Fixed-Oxide Charge3.2.2.3 Oxide-Trapped Charge3.2.2.4 Mobile Ionic Charge3.2.3 Flat Band Voltage3.2.4 Effect of Band Bending on the Semiconductor Surface3.3 MOS Capacitor under Applied Bias3.3.1 Accumulation3.3.2 Depletion3.3.3 Inversion3.4 MOS Capacitor Theory3.4.1 Formulation of Poisson’s Equation in Terms of Band-Bending Potential3.4.2 Electrostatic Potentials and Charge Distribution3.4.2.1 MOS Capacitor at Depletion: Depletion Approximation3.4.2.2 MOS Capacitor at Inversion3.5 Capacitance of MOS Structure3.5.1 Low Frequency C–V Characteristics3.5.1.1 Accumulation3.5.1.2 Flat Band3.5.1.3 Depletion3.5.1.4 Inversion3.5.2 Intermediate and High Frequency C–V Characteristics3.5.3 Deep Depletion C–V Characteristics3.5.4 Deviation from Ideal C–V Curves3.5.5 Polysilicon Depletion Effect on C–V Curves3.6 SummaryExercises
4. Large Geometry MOSFET Compact Models
4.1 Introduction4.2 Overview of MOSFET Devices4.2.1 Basic Features of MOSFET Devices4.2.2 MOSFET Device Operation4.3 MOSFET Threshold Voltage Model4.4 MOSFET Drain Current Model4.4.1 Drain Current Formulation4.4.2 Pao-Sah Model4.4.3 Charge-Sheet Model4.4.3.1 Drift Component of Drain Current4.4.3.2 Diffusion Component of Drain Current4.4.4 Regional Drain Current Model4.4.4.1 Core Model4.4.4.2 Bulk-Charge Model4.4.4.3 Square Root Approximation of Bulk-Charge Model4.4.4.4 Subthreshold Region Drain Current Model4.4.4.5 Limitations of Regional Drain Current Model4.5 SummaryExercises
5. Compact Models for Small Geometry MOSFETs
5.1 Introduction5.2 Threshold Voltage Model5.2.1 Effect of Nonuniform Channel Doping on Threshold Voltage5.2.1.1 Threshold Voltage Modeling for Nonuniform Vertical Channel Doping Profile5.2.1.2 Threshold Voltage Modeling for Nonuniform Lateral Channel Doping Profile5.2.2 Small Geometry Effect on Threshold Voltage Model5.2.2.1 Threshold Voltage Model for Short Channel MOSFET Devices5.2.2.2 Threshold Voltage Modeling for Narrow Channel MOSFET Devices5.3 Drain Current Model5.3.1 Surface Mobility Model5.3.2 Subthreshold Region Drain Current Model5.3.3 Linear Region Drain Current Model5.3.4 Saturation Region Drain Current Model5.3.5 Bulk-Charge Effect5.3.6 Output Resistance5.3.7 Unified Drain Current Equation5.3.8 S/D Parasitic Series Resistance5.3.9 Polysilicon Gate Depletion5.3.10 Temperature Dependence5.4 Substrate Current Model5.4.1 Gate-Induced Drain Leakage Body Current Model5.4.2 Gate Current Model5.5 SummaryExercises
6. MOSFET Capacitance Models
6.1 Introduction6.2 Basic MOSFET Capacitance Model6.2.1 Intrinsic Charges and Capacitances6.2.2 Meyer Model6.2.2.1 Strong Inversion6.2.2.2 Weak Inversion6.2.3 Limitations of Meyer Model6.3 Charge-Based Capacitance Model6.3.1 Long Channel Charge Model6.3.1.1 Strong Inversion6.3.1.2 Weak Inversion6.3.1.3 Accumulation6.3.2 Long Channel Capacitance Model6.3.3 Short Channel Charge Model6.3.4 Short Channel Capacitance Model6.4 Gate Overlap Capacitance Model6.5 Limitations of the Quasistatic Model6.6 S/D pn-Junction Capacitance Model6.6.1 Source-Body pn-Junction Diode6.6.2 Drain-Body Junction Diode6.7 SummaryExercises
7. Compact MOSFET Models for RF Applications
7.1 Introduction7.2 MOSFET Noise Models7.2.1 Fundamental Sources of Noise7.2.2 Thermal Noise7.2.2.1 Physical Mechanism of Thermal Noise7.2.2.2 Thermal Noise Model7.2.3 Flicker Noise7.2.3.1 Physical Mechanism of Flicker Noise7.2.3.2 Flicker Noise Model7.3 NQS Effect7.3.1 Modeling NQS Effect in MOSFETs7.4 Modeling Parasitic Elements for RF Applications7.4.1 Modeling Gate Resistance7.4.2 Modeling Substrate Network7.4.3 MOSFET RF Model for GHz Applications7.5 SummaryExercises
8. Modeling Process Variability in Scaled MOSFETs
8.1 Introduction8.2 Sources of Front-End Process Variability8.2.1 Systematic or Global Process Variability8.2.2 Random or Local Process Variability8.2.2.1 Random Discrete Doping8.2.2.2 Line-Edge Roughness8.2.2.3 Oxide Thickness Variation8.2.2.4 Other Sources Process Variability8.3 Characterization of Parametric Variability in MOSFETs8.3.1 Random Variability8.3.2 Systematic Variability8.4 Conventional Process Variability Modeling for Circuit CAD8.4.1 Worst-Case Fixed Corner Models8.4.2 Statistical Corner Models8.4.3 Process Parameters–Based Compact Variability Modeling8.5 Statistical Compact Modeling8.5.1 Determination of Process Variability-Sensitive MOSFET Device Parameters8.5.1.1 Selection of Local Process Variability-Sensitive Device Parameters8.5.1.2 Selection of Global Process Variability-Sensitive Device Parameters8.5.2 Mapping Process Variability-Sensitive Device Parameters to Compact Model Parameters8.5.2.1 Mapping Local Process Variability-Sensitive Device Parameters to Compact Model Parameters8.5.2.2 Mapping Global Process Variability-Sensitive Device Parameters to Compact Model Parameters8.5.3 Determination of Variance for Process Variability-Sensitive Compact Model Parameters8.5.3.1 Variance of Local Process Variability-Sensitive Compact Model Parameters8.5.3.2 Variance of the Global Process Variability-Sensitive Compact Model Parameters8.5.4 Formulation of Compact Model for Process Variability-Aware Circuit Design8.5.5 Simulation Results and Discussions8.6 Mitigation of the Risk of Process Variability in VLSI Circuit Performance8.7 SummaryExercises
9. Compact Models for Ultrathin Body FETs
9.1 Introduction9.2 Multigate Device Structures9.2.1 Bulk-Multigate Device Structure9.2.2 UTB-SOI Device Structure9.3 Common Multiple-Gate FinFET Model9.3.1 Core Model: Poisson-Carrier Transport9.3.1.1 Electrostatics9.3.1.2 Drain Current Model9.3.2 Modeling Physical Effects of Real Device9.3.2.1 Short Channel Effects9.3.2.2 Quantum Mechanical Effects9.3.2.3 Mobility Degradation9.3.2.4 Series Resistances9.4 Independent Multiple-Gate FET Model9.4.1 Electrostatics9.4.2 Drain Current Model9.5 Dynamic Model9.5.1 Common Multigate C–V Model9.5.2 Independent Multigate C–V Model9.6 SummaryExercises
10. Beyond-CMOS Transistor Models: Tunnel FETs
10.1 Introduction10.2 Basic Features of TFETs10.3 Basic Theory of TFET Operation10.3.1 Energy Band Diagram10.3.2 Tunneling Mechanism10.3.3 Device Characteristics10.3.4 Subthreshold Swing10.4 TFET Design Considerations10.5 Compact TFET Models10.5.1 Threshold Voltage Model10.5.2 Drain Current Model10.5.2.1 Ideal Drain Current Model10.5.2.2 Modeling the Channel Transports Using Drain MOSFET10.5.2.3 Modeling the Channel Transports Using Source Resistance10.6 SummaryExercises
11. Bipolar Junction Transistor Compact Models
11.1 Introduction11.2 Basic Features of BJTs11.3 Basic Operation of BJTs11.4 Mode of Operations of BJTs11.5 Compact BJT Model11.5.1 Basic DC Model: EM111.5.1.1 Linear Hybrid-π Small Signal Model11.5.2 Enhancement of the Basic Model11.5.2.1 Modeling Parasitic Circuit Elements11.5.2.2 Limitations of Basic Model11.5.3 Modeling Carrier Recombination in the Depletion Regions11.5.4 Modeling Base-Width Modulation and High-Level Injection11.5.4.1 Components of Injected Base Charge11.5.5 Summary of Compact BJT Model11.6 SummaryExercises
12. Compact Model Library for Circuit Simulation
12.1 Introduction12.2 General Approach to Generate Compact Device Model12.2.1 Data Collection12.2.1.1 Selection of Devices12.2.1.2 Selection of Device Characteristics12.2.2 Data Fitting to Extract Compact Model Parameters12.2.3 Generation of Parameter Files12.2.4 Generation of Compact Model Library12.2.4.1 Modeling Systematic Process Variability12.2.4.2 Modeling Mismatch12.2.4.3 Generate Model Card12.2.5 Model Validation12.3 Model Usage12.4 SummarySample Model Cards
References
Index

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Compact Models for Integrated Circuit Design

by Samar K. Saha

Become an O’Reilly member and get unlimited access to this title plus top books and audiobooks from O’Reilly and nearly 200 top publishers, thousands of courses curated by job role, 150+ live events each month,
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