December 2011
Intermediate to advanced
436 pages
18h 7m
English
book
Real-Time Digital Signal Processing from MATLAB® to C with the TMS320C6x DSPs, Second Edition, 2nd Edition
by Thad B. Welch, Cameron H.G. Wright, Michael G. Morrow
Content preview from Real-Time Digital Signal Processing from MATLAB® to C with the TMS320C6x DSPs, Second Edition, 2nd Edition
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258 CHAPTER 15. PROJECT 6: PHASE-LOCKED LOOP
Figure 15.15: A typical transient response of the system to a 750 Hz message modulated
(AM-DSB-SC) with a 12 kHz carrier.
2. Design and implement an algorithm that detects, then provides some indication to
the user, when the PLL is locked and tracking the input signal.
3. There are three significant computational inefficiencies (bottlenecks) in the PLL ISR.
Profile the ISR code and identify these bottlenecks.
4. Suggest possible improvements that minimize or remove these bottlenecks.
5. Implement at least one of your improvements and calculate the computational savings
of your new code.
6. Implement a PLL using ...
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I'm always learning. So when I got on to O'Reilly, I was like a kid in a candy store. There are playlists. There are answers. There's on-demand training. It's worth its weight in gold, in terms of what it allows me to do.