ASIC and FPGA Verification

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Testbenches for

Component Models

At least half the work of creating a component model is in the verification. The

purpose of component models is the verification of board- or system-level designs,

but the component models must first be verified themselves. This is done using a

testbench. Writing the testbench is often as much work as writing the model, some-

times even more. The quality of the testbench may determine the quality of the

model.

The topic of testbenches is a large one. Books have been devoted to it. This

chapter will discuss only a few aspects of particular interest to those modeling

components.

17.1 About Testbenches

The purpose ...