ASIC and FPGA Verification

Parts I and II covered the construction of basic models of simple components with

a focus on using various packages as resources. In Part III we build on this foun-

dation by demonstrating how to write complete models for small- and medium-

scale integrated circuits. Components with registers are the primary focus: With

registers come additional constraint requirements, such as conditional timings

and negative timing constraints. The structure and syntax of timing files are also

covered.

Chapter 9 explores the requirements for modeling devices containing latches

and registers. New generics and their associated timing checks are introduced. The

use of ...