ASIC and FPGA Verification

13.3 A Wrapper for Verilog RTL

It is possible your RTL model is written in Verilog. Verilog works fine for synthesis,

but you may find VHDL is better supported for board-level verification. If so, don’t

worry. The exact same wrapper will work for Verilog RTL. As long as you have a

bilingual simulator and you make the port names in the component declaration

match those in your Verilog module, there is no difference:

COMPONENT fpga299

PORT (

CLR_L : IN std_logic;

OE1_L : IN std_logic;

OE2_L : IN std_logic;

S0 : IN std_logic;

S1 : IN std_logic;

CLK : IN std_logic;

IO : INOUT std_logic_vector(7 downto 0);

Q0 : OUT std_logic;

Q7 : OUT std_logic;

SL : IN std_logic;