ASIC and FPGA Verification

Parameters of Mode IN

TestSignal, the value of the test signal. For this procedure TestSignal must

be std_logic. It should be a delayed input signal.

TestSignalName, the name of the test signal. It is of type STRING and will be

used in any messages generated by the procedure. You should supply a name

the user will recognize.

TestDelay, not shown. This is the model’s internal delay associated with

TestSignal. It is used only in models having negative timing constraints. It is of

type TIME. If a value is not provided, it defaults to zero.

Period, the minimum period allowed between consecutive rising (‘P’) or

falling (‘F’) transitions. It is of type TIME ...