ASIC and FPGA Verification

SDF

conditional delays in, 149–150

generation, 259–261

keywords, 62

mapping to VITAL, 152–153

to netlist mapping, 61

operators for expressions in, 151

to VITAL symbol mapping, 153

SDF capabilities, 52–57

circuit delays, 52–55

timing checks, 55–57

SDF constructs, example usage of, 57

SDF files, 47–52

cells, 50

generating, 184–185

headers, 48–50

sample, 48

timing specifications, 50–52

SDF, introduction to, 47–58

SDF capabilities, 52–57

SDF files, 47–52

SDRAMs (Synchronous Dynamic RAMs), 209,

244–249

sections

concurrent procedure, 70

declarative, 66–67

example of VITAL process declarative, 67

functionality, 68–69

path delay, 69

timing check, 67–68

serial sampling 12-bit A/D converter ...