ASIC and FPGA Verification

SETUP, specifies a setup constraint value. It is followed by the names of two

input ports. The first is the test port, usually address or data, and the second is

the reference port, usually a clock. Finally there is a triplet. Because we are only

interested in worst-case constraints, not min, typ, or max, the three values are

identical. Alternatively, only a single value could be supplied.

(SETUP A CLKAB (6:6:6))

HOLD, identical to SETUP except it specifies a hold constraint value.

(HOLD A CLKAB (.5:.5:.5))

WIDTH, defines a minimum pulse width value. A single port name is preceded

by an edge specifier. Finally the constraint value is given. The posedge specifi- ...