ASIC and FPGA Verification

HoldHigh => thold_S0_CLK,

HoldLow => thold_S0_CLK,

CheckEnabled => (S1nwv = ‘1’),

RefTransition => ‘/’,

HeaderMsg => InstancePath & “/std869”,

TimingData => TD_S0_CLK_S1_EQ_1,

XOn => XOn,

MsgOn => MsgOn,

Violation => Tviol_S0_CLK_S1_EQ_1 );

In this case, are there two levels of selection. The first is controlled by the Check-

Enabled parameter. It is based on the value of S1nwv and determines which pro-

cedure call is executed. Next, within each procedure call distinct setup constraint

values are selected for the case where S0_ipd is high and S0_ipd is low. This is

done through the SetupHigh and SetupLow parameters.

10.6 Summary

There are many situations where ...