ASIC and FPGA Verification

Because in the event of a timing violation circuit behavior is unknown, the table

will specify an ‘X’ in that situation, as shown in Figure 7.8. Now the table is com-

plete. Although the data sheet may have described the part with a table of 3 or 4

rows, the state table for our model has 8 rows in order to correctly cover all the

nonspecified conditions and to avoid excess pessimism.

7.5 Memory Tables

The 2000 revision of the VITAL standard added the VITALMemory package, which

includes the VitalMemoryTable procedure. It can be thought of as an extension

of the VitalStateTable that has been specialized for describing static memories.

VITAL memory tables ...