ASIC and FPGA Verification

To add backannotation of the FPGA with maximum timing values, the command

is expanded to

vsim -sdftyp testbench/uut=myboard.sdf -sdfmax testbench/uut/u26=myfpga.sdf

testbench

The added option -sdfmax tells the simulator to perform another backannotation

using maximum timing values. This backannotation is to be applied to instance

u26 in UUT (in the testbench). The SDF file to use is named myfpga.sdf.

More than one SDF file can be backannotated to a single object. If we had an

SDF file with the interconnect delays for the board, it could also be applied to test-

bench/UUT.

12.8 Summary

External timing files allow us to write technology-independent (timing) ...