Verilog supports two types of multiway branching and five looping constructs. SystemVerilog adds two more types of loops that are unsupported in standard Verilog. Loops are more commonly used in verification than circuit design, but most looping constructs are synthesizable as long as the number of iterations is fixed at compile time. Multiway branching is fundamental for all high-level circuit descriptions as well as verification. All these constructs except generate loops are only legal inside of functional blocks. Generate statements can exist only outside of any blocks, although they still must be inside of a module.