Chapter 7

Synchronization

Abstract

The previous chapters have covered the parts of Verilog and SystemVerilog that are useful for circuit design. Using them to create reliable circuits, however, requires more expertise. Lack of understanding of asynchronous interfaces is one of the most common sources of failures in digital circuits. This chapter examines the theoretical basis for circuit failures due to timing errors and supplies a set of solutions that can be applied to different types of synchronizing challenges.

Keywords

latches

metastability

MTBF

resolution time

violation

FIFO

serial bus

parallel bus

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