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Digital Integrated Circuit Design Using Verilog and Systemverilog
book

Digital Integrated Circuit Design Using Verilog and Systemverilog

by Ronald W. Mehler
September 2014
Intermediate to advanced content levelIntermediate to advanced
448 pages
9h 45m
English
Newnes
Content preview from Digital Integrated Circuit Design Using Verilog and Systemverilog
Chapter 10

Design for testability

Abstract

Once a design has been completed, layout files are sent out for fabrication. Despite the best efforts of the foundry, not all the devices produced will be usable. Some will be defective. The bad ones should be screened out through testing.

Keywords

fault

defect

stuck at

modeling

scan

JTAG

BIST

LFSR

Once a design has been completed, layout files are sent out for fabrication. Despite the best efforts of the foundry, not all the devices produced will be usable. Some will be defective. ...

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Publisher Resources

ISBN: 9780124080591