September 2014
Intermediate to advanced
448 pages
9h 45m
English
Content preview from Digital Integrated Circuit Design Using Verilog and Systemverilog
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Chapter 10
Design for testability
Abstract
Once a design has been completed, layout files are sent out for fabrication. Despite the best efforts of the foundry, not all the devices produced will be usable. Some will be defective. The bad ones should be screened out through testing.
Keywords
fault
defect
stuck at
modeling
scan
JTAG
BIST
LFSR
Once a design has been completed, layout files are sent out for fabrication. Despite the best efforts of the foundry, not all the devices produced will be usable. Some will be defective. ...
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I'm always learning. So when I got on to O'Reilly, I was like a kid in a candy store. There are playlists. There are answers. There's on-demand training. It's worth its weight in gold, in terms of what it allows me to do.