Digital Integrated Circuit Design Using Verilog and Systemverilog

Chapter 6

Subroutines and interfaces

Abstract

Verilog has two types of subroutines, tasks and functions. Each has its limitations and advantages, which will be discussed in this chapter. The most fundamental difference between tasks and functions is that functions cannot contain any type of delay, whereas tasks do not share this restriction.

Keywords

task

function

reference

interface

modport

include

import

Outline

 Subroutines 172

 Tasks 172

 Functions 181

 Parameters in subroutines 186

 Managing subroutines 187

 Interfaces 191

 Interface modports 195

 Summary 198

Verilog has two types of subroutines, tasks and functions. Each has its limitations and advantages, which will be discussed in this chapter. The most fundamental difference ...