Skip to Main Content
Digital Integrated Circuit Design Using Verilog and Systemverilog
book

Digital Integrated Circuit Design Using Verilog and Systemverilog

by Ronald W. Mehler
September 2014
Intermediate to advanced content levelIntermediate to advanced
448 pages
9h 45m
English
Newnes
Content preview from Digital Integrated Circuit Design Using Verilog and Systemverilog
Chapter 6

Subroutines and interfaces

Abstract

Verilog has two types of subroutines, tasks and functions. Each has its limitations and advantages, which will be discussed in this chapter. The most fundamental difference between tasks and functions is that functions cannot contain any type of delay, whereas tasks do not share this restriction.

Keywords

task

function

reference

interface

modport

include

import

Verilog has two types of subroutines, tasks and functions. Each has its limitations and advantages, which will be discussed in this chapter. The most fundamental difference ...

Become an O’Reilly member and get unlimited access to this title plus top books and audiobooks from O’Reilly and nearly 200 top publishers, thousands of courses curated by job role, 150+ live events each month,
and much more.
Start your free trial

You might also like

Digital VLSI Design and Simulation with Verilog

Digital VLSI Design and Simulation with Verilog

Suman Lata Tripathi, Sobhit Saxena, Sanjeet K. Sinha, Govind S. Patel

Publisher Resources

ISBN: 9780124080591