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Digital Integrated Circuit Design Using Verilog and Systemverilog by Ronald W. Mehler

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Chapter 11

Library modeling

Abstract

Once a design has been verified, the next step is logic synthesis. Logic synthesis produces a technology-dependent netlist implementation of the design. Such a netlist needs to include instances of cell models. All the cell models for a given target technology are gathered together into a library. This chapter deals with creating cell models for a component library.

Keywords

component

library

cell model

specify block

user-defined primitive

timing checks

Once a design has been verified, the next step is logic synthesis. Logic ...

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