Skip to Main Content
Digital Integrated Circuit Design Using Verilog and Systemverilog
book

Digital Integrated Circuit Design Using Verilog and Systemverilog

by Ronald W. Mehler
September 2014
Intermediate to advanced content levelIntermediate to advanced
448 pages
9h 45m
English
Newnes
Content preview from Digital Integrated Circuit Design Using Verilog and Systemverilog
Chapter 11

Library modeling

Abstract

Once a design has been verified, the next step is logic synthesis. Logic synthesis produces a technology-dependent netlist implementation of the design. Such a netlist needs to include instances of cell models. All the cell models for a given target technology are gathered together into a library. This chapter deals with creating cell models for a component library.

Keywords

component

library

cell model

specify block

user-defined primitive

timing checks

Once a design has been verified, the next step is logic synthesis. Logic ...

Become an O’Reilly member and get unlimited access to this title plus top books and audiobooks from O’Reilly and nearly 200 top publishers, thousands of courses curated by job role, 150+ live events each month,
and much more.
Start your free trial

You might also like

Digital VLSI Design and Simulation with Verilog

Digital VLSI Design and Simulation with Verilog

Suman Lata Tripathi, Sobhit Saxena, Sanjeet K. Sinha, Govind S. Patel

Publisher Resources

ISBN: 9780124080591