Digital Integrated Circuit Design Using Verilog and Systemverilog

Index

A

Address/Data bus (ADBUS.DATA), 191

Address Decoder Faults, 323

Addressing algorithm

block diagram of, 234

Aggressor cell, 323

Alternative algorithm, 234

Always_latch construct signals, 50

Ambiguous signals, 87

AND gate, 19, 394

ANDGATE1, 37

model, two-input, 345

resolution, 88

symbol of, 394

truth able, 394

AND-OR-INVERT cell, 344

function, 340

models, 346

with distributed and lumped delays, 341

with full connection specify block, 344

Application-specific integrated circuit (ASIC)

designers, 6, 261

design methodology, 7, 249

libraries, 262

style, 262

vs. FPGA, 261

ASIC coding style for D flipflop, 262

FPGA style flipflop, 263

Application-specific processor, 264

Arbitrary time, 208

Architectural choices, 261

area and speed optimization, ...