Digital VLSI Design and Simulation with Verilog

4 Programming Techniques in Verilog I

4.1 Programming Techniques in Verilog I

Verilog HDL is a synthesized tool through which circuit designers can design their desired circuit in their own way. In Verilog, the digital circuit can be described in terms of a network of digital components. Verilog programming has the same C language type syntax. Verilog is used to describe hardware whereas C language is considered software language. In Verilog, the statements are concurrent compared to other languages. In other languages, the statements execute sequentially. The basic building block for writing Verilog code is the module statement. In a module definition, all input as well as output of the desired circuit is defined. Synthesized Verilog codes are mapped to the actual hardware logic gates of the circuits. In this chapter, the gate-level modeling of the circuit is described with the help of different types of circuit.

4.2 Gate-Level Model of Circuits

In gate-level modeling, logic gates used in the circuits are called from the available library of Verilog HDL. In this modeling, the logic gates used have one-to-one relations inside the hardware schematic. The gate-level model is considered as the lowest level of design model.

Example 1: A basic logic circuit at gate level is shown in Figure 4.1.

Figure 4.1 Logic circuit.

Verilog Code:

module Circuit(A,B,F);
input A, B;
output F; ...