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Digital VLSI Design and Simulation with Verilog

Name: Digital VLSI Design and Simulation with Verilog
ISBN: 9781119778042

by Suman Lata Tripathi, Sobhit Saxena, Sanjeet K. Sinha, Govind S. Patel

December 2021

Intermediate to advanced

224 pages

4h 13m

English

Wiley

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Cover
Title page
Copyright
Preface
About the Authors
1 Combinational Circuit Design
1.1 Logic Gates1.1.1 Universal Gate Operation1.1.2 Combinational Logic Circuits1.2 Combinational Logic Circuits Using MSI1.2.1 Adders1.2.2 Multiplexers1.2.3 De-multiplexer1.2.4 Decoders1.2.5 Multiplier1.2.6 Comparators1.2.7 Code Converters1.2.8 Decimal to BCD EncoderReview QuestionsMultiple Choice QuestionsReference
2 Sequential Circuit Design
2.1 Flip-flops (F/F)2.1.1 S-R F/F2.1.2 D F/F2.1.3 J-K F/F2.1.4 T F/F2.1.5 F/F Excitation Table2.1.6 F/F Characteristic Table2.2 Registers2.2.1 Serial I/P and Serial O/P (SISO)2.2.2 Serial Input and Parallel Output (SIPO)2.2.3 Parallel Input and Parallel Output (PIPO)2.2.4 Parallel Input and Serial Output (PISO)2.3 Counters2.3.1 Synchronous Counter2.3.2 Asynchronous Counter2.3.3 Design of a 3-Bit Synchronous Up-counter2.3.4 Ring Counter2.3.5 Johnson Counter2.4 Finite State Machine (FSM)2.4.1 Mealy and Moore Machine2.4.2 Pattern or Sequence DetectorReview QuestionsMultiple Choice QuestionsReference
3 Introduction to Verilog HDL
3.1 Basics of Verilog HDL3.1.1 Introduction to VLSI3.1.2 Analog and Digital VLSI3.1.3 Machine Language and HDLs3.1.4 Design Methodologies3.1.5 Design Flow3.2 Level of Abstractions and Modeling Concepts3.2.1 Gate Level3.2.2 Dataflow Level3.2.3 Behavioral Level3.2.4 Switch Level3.3 Basics (Lexical) Conventions3.3.1 Comments3.3.2 Whitespace3.3.3 Identifiers3.3.4 Escaped Identifiers3.3.5 Keywords3.3.6 Strings3.3.7 Operators3.3.8 Numbers3.4 Data Types3.4.1 Values3.4.2 Nets3.4.3 Registers3.4.4 Vectors3.4.5 Integer Data Type3.4.6 Real Data Type3.4.7 Time Data Type3.4.8 Arrays3.4.9 Memories3.5 Testbench ConceptMultiple Choice QuestionsReferences
4 Programming Techniques in Verilog I
4.1 Programming Techniques in Verilog I4.2 Gate-Level Model of Circuits4.3 Combinational Circuits4.3.1 Adder and Subtractor4.3.2 Multiplexer and De-multiplexer4.3.3 Decoder and Encoder4.3.4 ComparatorReview QuestionsMultiple Choice QuestionsReferences
5 Programming Techniques in Verilog II
5.1 Programming Techniques in Verilog II5.2 Dataflow Model of Circuits5.3 Dataflow Model of Combinational Circuits5.3.1 Adder and Subtractor5.3.2 Multiplexer5.3.3 Decoder5.3.4 Comparator5.4 Testbench5.4.1 Dataflow Model of the Half Adder and Testbench5.4.2 Dataflow Model of the Half Subtractor and Testbench5.4.3 Dataflow Model of 2 × 1 Mux and Testbench5.4.4 Dataflow Model of 4 × 1 Mux and Testbench5.4.5 Dataflow Model of 2-to-4 Decoder and TestbenchReview QuestionsMultiple Choice QuestionsReferences

6 Programming Techniques in Verilog II
6.1 Programming Techniques in Verilog II6.2 Behavioral Model of Combinational Circuits6.2.1 Behavioral Code of a Half Adder Using If-else6.2.2 Behavioral Code of a Full Adder Using Half Adders6.2.3 Behavioral Code of a 4-bit Full Adder (FA)6.2.4 Behavioral Model of Multiplexer Circuits6.2.5 Behavioral Model of a 2-to-4 Decoder6.2.6 Behavioral Model of a 4-to-2 Encoder6.3 Behavioral Model of Sequential Circuits6.3.1 Behavioral Modeling of the D-Latch6.3.2 Behavioral Modeling of the D-F/F6.3.3 Behavioral Modeling of the J-K F/F6.3.4 Behavioral Modeling of the D-F/F Using J-K F/F6.3.5 Behavioral Modeling of the T-F/F Using J-K F/F6.3.6 Behavior Modeling of an S-R F/F Using J-K F/FReview QuestionsMultiple Choice QuestionsReferences
7 Digital Design Using Switches
7.1 Switch-Level Model7.2 Digital Design Using CMOS Technology7.3 CMOS Inverter7.4 Design and Implementation of the Combinational Circuit Using Switches7.4.1 Types of Switches7.4.2 CMOS Switches7.4.3 Resistive Switches7.4.4 Bidirectional Switches7.4.5 Supply and Ground Requirements7.5 Logic Implementation Using Switches7.5.1 Digital Design with a Transmission Gate7.6 Implementation with Bidirectional Switches7.6.1 Multiplexer Using Switches7.7 Verilog Switch-Level Description with Structural-Level Modeling7.8 Delay Model with SwitchesReview QuestionsMultiple Choice QuestionsReferences
8 Advance Verilog Topics
8.1 Delay Modeling and Programming8.1.1 Delay Modeling8.1.2 Distributed-Delay Model8.1.3 Lumped-Delay Model8.1.4 Pin-to-Pin-Delay Model8.2 User-Defined Primitive (UDP)8.2.1 Combinational UDPs8.2.2 Sequential UDPs8.2.3 Shorthands in UDP8.3 Task and Function8.3.1 Difference between Task and Function8.3.2 Syntax of Task and Function Declaration8.3.3 Invoking Task and Function8.3.4 Examples of Task Declaration and Invocation8.3.5 Examples of Function Declaration and InvocationReview QuestionsMultiple Choice QuestionsReferences
9 Programmable and Reconfigurable Devices
9.1 Logic Synthesis9.1.1 Technology Mapping9.1.2 Technology Libraries9.2 Introduction of a Programmable Logic Device9.2.1 PROM, PAL and PLA9.2.2 SPLD and CPLD9.3 Field-Programmable Gate Array9.3.1 FPGA Architecture9.4 Shannon’s Expansion and Look-up Table9.4.1 2-Input LUT9.4.2 3-Input LUT9.5 FPGA Families9.6 Programming with FPGA9.6.1 Introduction to Xilinx Vivado Design Suite for FPGA-Based Implementations9.7 ASIC and Its ApplicationsReview QuestionsMultiple Choice QuestionsReferences
10 Project Based on Verilog HDLs
10.1 Project Based on Combinational Circuit Design Using Verilog HDL10.1.1 Full Adder Using Switches at Structural Level Model10.1.2 Ripple-Carry Full Adder (RCFA)10.1.3 4-bit Carry Look-ahead Adder (CLA)10.1.4 Design of a 4-bit Carry Save Adder (CSA)10.1.5 2-bit Array Multiplier10.1.6 2 × 2 Bit Division Circuit Design10.1.7 2-bit Comparator10.1.8 16-bit Arithmetic Logic Unit10.1.9 Design and Implementation of 4 × 16 Decoder Using 2 × Decoder10.2 Project Based on Sequential Circuit Design Using Verilog HDL10.2.1 Design of 4-bit Up/down Counter10.2.2 LFSR Based 8-bit Test Pattern Generator10.3 Counter Design10.3.1 Random Counter that Counts Sequence like 2,4,6,8,2,8…and so On10.3.2 Use of Task at the Behavioral-Level Model10.3.3 Traffic Signal Light Controller10.3.4 Hamming Code(h,k) Encoder/DecoderReview QuestionsMultiple Choice QuestionsReferences
11 SystemVerilog
11.1 Introduction11.2 Distinct Features of SystemVerilog11.2.1 Data Types11.2.2 Arrays11.2.3 Typedef11.2.4 Enum11.3 Always_type11.4 $log2c() Function11.5 System-Verilog as a Verification LanguageReview QuestionsMultiple Choice QuestionsReference
Index
End User License Agreement

Content preview from Digital VLSI Design and Simulation with Verilog

Digital VLSI Design and Simulation with Verilog

Dr. Suman Lata Tripathi

Lovely Professional University, Phagwara, Punjab, India

Dr. Sobhit Saxena

Lovely Professional University, Phagwara, Punjab, India

Dr. Sanjeet Kumar Sinha

Lovely Professional University, Phagwara, Punjab, India

Dr. Govind Singh Patel

IIMT College of Engineering, Greater Noida, UP, India

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Digital Integrated Circuit Design Using Verilog and Systemverilog

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Digital VLSI Design and Simulation with Verilog

by Suman Lata Tripathi, Sobhit Saxena, Sanjeet K. Sinha, Govind S. Patel

Digital VLSI Design and Simulation with Verilog

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