Digital VLSI Design and Simulation with Verilog
by Suman Lata Tripathi, Sobhit Saxena, Sanjeet K. Sinha, Govind S. Patel
About the Authors
Dr. Suman Lata Tripathi completed her PhD in the area of microelectronics and VLSI from Motilal Nehru National Institute of Technology, Allahabad. She obtained her M.Tech in Electronics Engineering from Uttar Pradesh Technical University, Lucknow and B.Tech in Electrical Engineering from Purvanchal University, Jaunpur. She is associated with Lovely Professional University as a Professor with more than 17 years of experience in academics. She has published more than 55 research papers in refereed IEEE, Springer, and IOP science journals and conferences. She has organized several workshops, summer internships, and expert lectures for students. She has worked as a session chair, conference steering committee member, editorial board member, and reviewer in international/national IEEE/Springer Journal and conferences. She received the “Research Excellence Award” in 2019 at Lovely Professional University. She received the best paper at IEEE ICICS-2018. She has edited more than 12 books/1 book series in different areas of electronics and electrical engineering. She is associated with editing work for top publishers including Elsevier, CRC, Taylor and Francis, Wiley-IEEE, SP Wiley, Nova Science, and Apple Academic Press. She also works as series editor for, “Smart Engineering Systems” CRC Press, Taylor and Francis. She is associated as a senior member IEEE, Fellow IETE and Life member of ISC and is continuously involved in different professional activities along with ...
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