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Digital VLSI Design and Simulation with Verilog
book

Digital VLSI Design and Simulation with Verilog

by Suman Lata Tripathi, Sobhit Saxena, Sanjeet K. Sinha, Govind S. Patel
December 2021
Intermediate to advanced
224 pages
4h 13m
English
Wiley
Content preview from Digital VLSI Design and Simulation with Verilog

Preface

Integrated circuits are now growing in importance in every electronic system that needs an efficient VLSI architecture design with low-power consumption, a compress chip area, speed, and operating frequency. The challenge for VLSI system designers is to optimize hardware-software integration for lowering the total cost of product acquisition. So, there is a demand for better technological solutions for advanced VLSI architectures that can be done through hardware description language (HDL). Verilog HDL is one of the programming languages that can provide better solutions in this new era of the VLSI industry. The prefabrication design and analysis of such advanced VLSI architecture can easily be implemented with Verilog HDL using available software tools such as Xilinx and Cadence.

This book mainly deals with the fundamental concepts of digital design along with their design verification with Verilog HDL. It will be a common source of knowledge for beginners as well as research-seeking students working in the area of VLSI design, covering fundamentals of digital design from switch level to FPGA-based implementation using hardware description language (HDL).

The book is summarized in 10 chapters. Chapters 1 and 2 describe the fundamental concepts behind digital circuit design including combinational and sequential circuit design. Chapters 3 to 8 focus on sequential and combinational circuit design using Verilog HDL at different levels of abstraction in Verilog coding. ...

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Publisher Resources

ISBN: 9781119778042Purchase Link