book

FPGA-based Implementation of Signal Processing Systems

by Roger Woods, John Mcallister, Gaye Lightbody, Ying Yi

December 2008

Intermediate to advanced

382 pages

13h 33m

English

Wiley

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Roger WoodsJohn McAllisterGaye LightbodyYing Yi
DSP and FPGAsAudienceOrganization
1.1 Introduction1.2 A Short History of the Microchip1.3 Influence of Programmability1.4 Challenges of FPGAsReferences
2.1 Introduction2.2 DSP System Basics2.3 DSP System Definitions2.4 DSP Transforms2.5 Filter Structures2.6 Adaptive Filtering2.7 Basics of Adaptive Filtering2.8 ConclusionsReferences
3.1 Introduction3.2 Number Systems3.3 Fixed-point and Floating-point3.4 Arithmetic Operations3.5 Fixed-point versus Floating-point3.6 ConclusionsReferences

4.1 Introduction4.2 Architecture and Programmability4.3 DSP Functionality Characteristics4.4 Processor Classification4.5 Microprocessors4.6 DSP Microprocessors (DSPμs)4.7 Parallel Machines4.8 Dedicated ASIC and FPGA Solutions4.9 ConclusionsReferences
5.1 Introduction5.2 Toward FPGAs5.3 Altera FPGA Technologies5.4 Xilinx FPGA Technologies5.5 Lattice ® FPGA Families5.6 Actel ® FPGA Technologies5.7 Atmel ® FPGA Technologies5.8 General Thoughts on FPGA TechnologiesReferences
6.1 Introduction6.2 Various Forms of the LUT6.3 Memory Availability6.4 Fixed Coefficient Design Techniques6.5 Distributed Arithmetic6.6 Reduced Coefficient Multiplier6.7 Final StatementsReferences
7.1 Introduction7.2 The Evolution of FPGA System Design7.3 Design Methodology Requirements for FPGA DSP7.4 System Specification7.5 IP Core Generation Tools for FPGA7.6 System-level Design Tools for FPGA7.7 ConclusionReferences
8.1 Introduction8.2 DSP Algorithm Characteristics8.3 DSP Algorithm Representations8.4 Basics of Mapping DSP Systems onto FPGAs8.5 Parallel Operation8.6 Hardware Sharing8.7 Application to FPGA8.8 ConclusionsReferences
9.1 Introduction of Behavioural Synthesis Tools9.2 IRIS Behavioural Synthesis Tool9.3 IRIS Retiming9.4 Hierarchical Design Methodology9.5 Hardware Sharing Implementation (Scheduling Algorithm) for IRIS9.6 Case Study: Adaptive Delayed Least-mean-squares Realization9.7 ConclusionsReferences
10.1 Motivation for Design for Reuse10.2 Intellectual Property (IP) Cores10.3 Evolution of IP Cores10.4 Parameterizable (Soft) IP Cores10.5 IP Core Integration10.6 ADPCM IP Core Example10.7 Current FPGA-based IP Cores10.8 SummaryReferences
11.1 Introduction11.2 Dataflow Modelling and Rapid Implementation for FPGA DSP Systems11.3 Rapid Synthesis and Optimization of Embedded Software from DFGs11.4 System-level Modelling for Heterogeneous Embedded DSP Systems11.5 Pipelined Core Design of MADF Algorithms11.6 System-level Design and Exploration of Dedicated Hardware Networks11.7 SummaryReferences
12.1 Introduction to Adaptive Beamforming12.2 Generic Design Process12.3 Adaptive Beamforming Specification12.4 Algorithm Development12.5 Algorithm to Architecture12.6 Efficient Architecture Design12.7 Generic QR Architecture12.8 Retiming the Generic Architecture12.9 Parameterizable QR Architecture12.10 Generic Control12.11 Beamformer Design Example12.12 SummaryReferences
13.1 Introduction13.2 Sources of Power Consumption13.3 Power Consumption Reduction Techniques13.4 Voltage Scaling in FPGAs13.5 Reduction in Switched Capacitance13.6 Data Reordering13.7 Fixed Coefficient Operation13.8 Pipelining13.9 Locality13.10 Application to an FFT Implementation13.11 ConclusionsReferences
14.1 Introduction14.2 Reconfigurable Systems14.3 Memory Architectures14.4 Support for Floating-point Arithmetic14.5 Future Challenges for FPGAsReferences