The choice of arithmetic has always been a key aspect for DSP implementation as it not only affects algorithmic performance, but also can impact system performance criteria, specifically area, speed and power consumption. For a DSP implementation on processor platforms, the choice of arithmetic becomes one of selecting the suitable platform, typically either a floating-point implementation or a fixed-point realization, with a subsequent choice of suitable wordlength for the fixed-point wordlength. However, with FPGA platforms, the choice of arithmetic can have a much wider impact on the performance cost right through the design process; though to be fair, architectural decisions made by FPGA vendors which can be seen in Chapter 5, tend to dominate arithmetic choice. Nonetheless, it is therefore worth considering and understanding arithmetic representations, in a little more detail.
A key requirement of DSP implementations is the availability of suitable processing elements, specifically adders and multipliers; however, some DSP algorithms, particularly adaptive filters, also require dedicated hardware for performing division and square root. The realization of these functions and indeed the choice of number systems, can have a major impact on hardware implementation quality. For example, it is well known that different DSP application domains, i.e. image processing, radar and speech, can have different levels of bit toggling not only in terms ...
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