FPGA-based Implementation of Signal Processing Systems

12

Adaptive Beamformer Example

Chapter 8 covered techniques to create efficient circuit architectures for SFG-based DSP systems. In this description, it was clear that many of the implementations could be created in a generic fashion with levels of pipelining used as a control parameter. Chapter 10 indicated that development of this generic architecture could be used across a wide range of applications if the parameterizable features could be used to drive efficient implementations across this range of parameters. This can only be achieved by identifying the key parameters of the DSP core functionality and then cleverly deriving a scalable architecture that will allow these parameters to be altered, whilst still producing linearly scaled performance. This requires a combination of high-level design optimizations and use of the techniques highlighted in Chapter 8.

This chapter is dedicated to the development of a QR-based IP core for adaptive beamforming. This example covers a number of stages, from the development of the mathematical algorithm through to the design of a scalable architecture. Focus is given to the techniques used to take the original architecture, then map and fold it down onto an efficient and scalable implementation, meeting the needs of the system requirements. Issues such as parameterizable timing and control management are also covered and how this relates to the earlier techniques.

The chapter is organized as follows. Section 12.1 gives an introduction to ...