Complex DSP Core Design for FPGA
Silicon technology is now at the stage where it is feasible to incorporate many millions of gates on a single square centimetre of silicon (Rowen 2002) with predictions of chip designs reaching over 2 billion transistors/cm2 by 2015 (Soderquist and Leeser 2004). This now permits extremely complex functions, which would previously be implemented as a collection of individual chips, to be built as a complete system-on-a-chip (SoC). The ability to encompass all parts of an application on the same piece of silicon presents advantages of lower power, greater reliability and reduced cost of manufacture. Consequently, increased pressure has been put on designers to meet ever-tightening time-to-market deadlines, now measured in months rather than years. The whole emphasis within the consumer market is to have high numbers of sales of cheaper products with a slimmer life span and in a much shorter time-to-market. Particularly with the onset of new standards such as H.264 and MPEG4 which are driving the growth of high-definition TV and mobile video.
This increasing chip density has enabled an expansion of FPGA capabilities with devices such as Xilinx's Virtex V and Altera's Stratix III offering full SoC functionality. With their vast expanse of usable gates comes the problem of developing increased complex systems to be implemented on these devices. Just as with ASIC development, as the complexity of the designs rises, the difference in the growth rate ...