Semiconductor Packaging

Semiconductor Packaging

by Andrea Chen, Randy Hsiao-Yu Lo
Released April 2016
Publisher(s): CRC Press
ISBN: 9781439862070

Read it now on the O’Reilly learning platform with a 10-day free trial.

O’Reilly members get unlimited access to books, live events, courses curated by job role, and more from O’Reilly and nearly 200 top publishers.

Start your free trial

Book description

In semiconductor manufacturing, understanding how various materials behave and interact is critical to making a reliable and robust semiconductor package. Semiconductor Packaging: Materials Interaction and Reliability provides a fundamental understanding of the underlying physical properties of the materials used in a semiconductor package. By tying together the disparate elements essential to a semiconductor package, the authors show how all the parts fit and work together to provide durable protection for the integrated circuit chip within as well as a means for the chip to communicate with the outside world. The text also covers packaging materials for MEMS, solar technology, and LEDs and explores future trends in semiconductor packages.

Table of contents

  1. Cover
  2. Half Title
  3. Title Page
  4. Copyright Page
  5. Table of Contents
  6. Preface
  7. Authors
  8. Partial list of abbreviations, acronyms, and symbols
  9. Section I: Semiconductor packages
    1. Chapter 1 History and background
      1. 1.1 Objectives
      2. 1.2 Introduction
      3. 1.3 Brief history
        1. 1.3.1 Hermetic packaging
        2. 1.3.2 Plastic packaging
      4. 1.4 Wire bonding process flow
      5. 1.5 Flip-chip process flow comparison
      6. 1.6 Equipment
      7. 1.7 Material interactions
      8. Bibliography
    2. Chapter 2 Package form factors and families
      1. 2.1 Objectives
      2. 2.2 Introduction
      3. 2.3 Package outline standardization
      4. 2.4 Leaded package families
        1. 2.4.1 Dual lead package family
      5. 2.5 Quad lead package family
      6. 2.6 Substrate-based package families
        1. 2.6.1 Ball grid array package family
      7. 2.7 Chip scale packages
        1. 2.7.1 Substrate-based chip scale packages
        2. 2.7.2 Quad flat no lead
      8. 2.8 Stacked-die package family
      9. 2.9 Package-on-package and related variations
      10. 2.10 Flip-chip packages
      11. 2.11 Wafer-level chip scale packages
      12. Bibliography
    3. Chapter 3 Surface-mount technology
      1. 3.1 Objectives
      2. 3.2 Introduction
      3. 3.3 Background
      4. 3.4 Package cracking or “popcorning”
      5. 3.5 Surface-mount packages: peripheral leads versus area array
      6. 3.6 Issues with advanced packaging
      7. 3.7 Current and trends
      8. 3.7.1 Lead-free and halogen free packaging
      9. Bibliography
    4. Chapter 4 Other packaging needs
      1. 4.1 Objectives
      2. 4.2 Introduction
      3. 4.3 Tape automated bonding
      4. 4.4 Micro electro-mechanical
      5. 4.5 Image sensor modules
      6. 4.6 Memory cards
      7. 4.7 Packaging needs for solar technology
      8. Bibliography
  10. Section II: Package reliability
    1. Chapter 5 Reliability testing
      1. 5.1 Introduction
      2. 5.2 Background
      3. 5.3 Examples of reliability tests
        1. 5.3.1 Preconditioning conditions
          1. 5.3.1.1 Package failure mode: package crack or popcorning
        2. 5.3.2 Temperature cycling and thermal shock
          1. 5.3.2.1 Package failure modes from temperature cycling and thermal shock
          2. 5.3.2.2 Package failure mode: delamination
        3. 5.3.3 High-temperature storage life
          1. 5.3.3.1 Package failure mode: intermetallics
        4. 5.3.4 Temperature-humidity-bias tests
          1. 5.3.4.1 Package failure mode: corrosion
      4. 5.4 Limitations of reliability testing
      5. Bibliography
  11. Section III: Materials used in semiconductor packaging
    1. Chapter 6 Polymers
      1. 6.1 Molding compounds
        1. 6.1.1 Objectives
        2. 6.1.2 Introduction
        3. 6.1.3 Background
        4. 6.1.4 Newer formulations
          1. 6.1.4.1 Biphenyl
          2. 6.1.4.2 Multifunctional
          3. 6.1.4.3 Aromatic resins
        5. 6.1.5 Technology challenges
          1. 6.1.5.1 Moldability
          2. 6.1.5.2 Glass transition temperature
          3. 6.1.5.3 Flexural modulus
          4. 6.1.5.4 Coefficient of thermal expansion
          5. 6.1.5.5 Stress index
        6. 6.1.6 Failure modes associated with molding compounds
          1. 6.1.6.1 Package cracking during solder reflow
          2. 6.1.6.2 Substrate postmold warpage
        7. 6.1.7 Future developments
          1. 6.1.7.1 “Green” molding compounds and changes to retardant additives
          2. 6.1.7.2 Molded
          3. 6.1.7.3 High-density packaging
          4. 6.1.7.4 Compatibility with copper wire bonding
      2. 6.2 Die attach adhesives
        1. 6.2.1 Objectives
        2. 6.2.2 Introduction
        3. 6.2.3 Background
        4. 6.2.4 Materials composition
          1. 6.2.4.1 Liquid epoxy resin
          2. 6.2.4.2 Silver flakes and other filler materials
          3. 6.2.4.3 Reactive epoxy diluents and solvents
          4. 6.2.4.4 Catalysts and hardeners
          5. 6.2.4.5 Other additives These components are usually proprietary and play an important role in producing a high-performance die attach adhesive.
        5. 6.2.5 Materials analysis
          1. 6.2.5.1 Glass transition temperature
          2. 6.2.5.2 Coefficient of thermal expansion
          3. 6.2.5.3 Thixotropic index
          4. 6.2.5.4 Ionic purity
        6. 6.2.6 Reliability and performance
          1. 6.2.6.1 Outgassing
          2. 6.2.6.2 Resin bleed
        7. 6.2.7 Future developments
          1. 6.2.7.1 Three-dimensional (3D) packaging
          2. 6.2.7.2 Lead-free and restriction of hazardous substances (RoHS)
          3. 6.2.7.3 Compatibility with copper wire bonding
          4. 6.2.7.4 Other developments
      3. 6.3 Underfill materials
        1. 6.3.1 Objectives
        2. 6.3.2 Introduction
        3. 6.3.3 What is underfill?
        4. 6.3.4 The purpose of underfill
        5. 6.3.5 The (standard) underfill process
        6. 6.3.6 Underfill properties
          1. 6.3.6.1 Glass transition temperature
          2. 6.3.6.2 Coefficient of thermal expansion
        7. 6.3.7 Alternate underfill processes
          1. 6.3.7.1 “No flow” underfill
          2. 6.3.7.2 Reworkable underfill
          3. 6.3.7.3 Preapplied underfill
          4. 6.3.7.4 Molded underfill
        8. 6.3.8 Areas of research and development
          1. 6.3.8.1 Maintaining capillary flow as features sizes shrink
          2. 6.3.8.2 Compatibility with lead-free bump process steps, including for copper pillar bumps
        9. 6.3.9 Failure modes
      4. 6.4 Organic substrates
        1. 6.4.1 Objectives
        2. 6.4.2 Introduction
        3. 6.4.3 Background
        4. 6.4.4 Ball grid arrays and chip scale packages
          1. 6.4.4.1 Microvias and high-density interconnect technology
        5. 6.4.5 Future developments
        6. Bibliography
    2. Chapter 7 Metals
      1. 7.1 Lead frames, heat spreaders, and heat sinks
        1. 7.1.1 Objectives
        2. 7.1.2 Introduction
        3. 7.1.3 Lead frames
        4. 7.1.4 Metals commonly used in lead frames and other components
          1. 7.1.4.1 Copper
          2. 7.1.4.2 Alloy42
          3. 7.1.4.3 Aluminum
        5. 7.1.5 Heat slugs, heat spreaders, and heat sinks
          1. 7.1.5.1 Heat slugs or spreaders
          2. 7.1.5.2 Heat sinks
        6. 7.1.6 Plating finishes
      2. 7.2 Bonding wires
        1. 7.2.1 Objectives
        2. 7.2.2 Introduction
        3. 7.2.3 Bonding wires
          1. 7.2.3.1 Gold
          2. 7.2.3.2 Copper
          3. 7.2.3.3 Aluminum
          4. 7.2.3.4 Other
        4. 7.2.4 Kirkendall effect
          1. 7.2.4.1 Gold-aluminum intermetallics and Kirkendall effect
          2. 7.2.4.2 Kirkendall effect for copper wire bonding on aluminum bond pads
        5. 7.2.5 Heat-affected zone phenomenon in bonding wire
          1. 7.2.5.1 How is the heat-affected zone created?
          2. 7.2.5.2 Effect of heat-affected zone on loop height
        6. 7.2.6 Other reliability issues
          1. 7.2.6.1 Copper wire bonding and corrosion
        7. 7.2.7 Materials analysis
          1. 7.2.7.1 Visual inspection
          2. 7.2.7.2 Bond etching
          3. 7.2.7.3 Bond pull
          4. 7.2.7.4 Ball shear tests
        8. 7.2.8 Recent developments
          1. 7.2.8.1 Copper wire bonding on nickel-palladium electroless plated bond pads
      3. 7.3 Solders
        1. 7.3.1 Objectives
        2. 7.3.2 Introduction
        3. 7.3.3 Types of solders
          1. 7.3.3.1 Lead-based
          2. 7.3.3.2 Lead-free
          3. 7.3.3.3 Gold-based
      4. 7.4 Wafer bumping
        1. 7.4.1 Objectives
        2. 7.4.2 Introduction
        3. 7.4.3 Bump metallurgies
          1. 7.4.3.1 “C4”
          2. 7.4.3.2 Electroplating
          3. 7.4.3.3 Electroless (UBM) plating and screen/ stencil printing solder
          4. 7.4.3.4 Lead-free bumping metallurgies
          5. 7.4.3.5 Alternative to solder bumping technologies
        4. 7.4.4 Under-bump metallurgy
          1. 7.4.4.1 Vacuum deposition
          2. 7.4.4.2 Electroplating
          3. 7.4.4.3 Electroless plating
        5. 7.4.5 Technical issues
        6. 7.4.6 Future directions
      5. Bibliography
    3. Chapter 8 Ceramics and glasses
      1. 8.1 Objectives
      2. 8.2 Introduction
      3. 8.3 Types of ceramics used in semiconductor packaging
        1. 8.3.1 Alumina
        2. 8.3.2 Beryllia
        3. 8.3.3 Aluminum nitride
        4. 8.3.4 Silicon carbide
        5. 8.3.5 Boron nitride
      4. 8.4 Types of glasses used in semiconductor packaging
        1. 8.4.1 Silver filled glass
        2. 8.4.2 Lead alkali borosilicate glass
      5. Bibliography
  12. Section IV:—The future
    1. Chapter 9 Trends and challenges
      1. 9.1 Objectives
      2. 9.2 Introduction
      3. 9.3 Copper interconnects and low-к dielectric materials
        1. 9.3.1 Copper interconnects
        2. 9.3.2 Dielectric materials
      4. 9.4 Dielectric constant requirements at each technology node
      5. 9.5 Future interconnect and dielectric materials
        1. 9.5.1 Interconnects for <22 nm
        2. 9.5.2 Dielectric materials for ≥22 nm
        3. 9.5.3 Dielectric materials for ≥22 nm
      6. 9.6 Future packaging options
        1. 9.6.1 Codesigning the chip with the package
        2. 9.6.2 Three-dimensional (3D) integration
        3. 9.6.3 Through-silicon vias
      7. Bibliography
    2. Chapter 10 Light-emitting diodes
      1. 10.1 Objectives
      2. 10.2 Introduction
      3. 10.3 Unique characteristics of light-emitting diode (LED) packaging needs
      4. 10.4 Reliability requirements for LED packages
      5. Bibliography
  13. Glossary
    1. Bibliography
  14. Appendix A: Analytical tools
    1. A.1 Introduction
    2. A.2 Types of analytical tools
    3. A.3 Nondestructive tools and tests
      1. A.3.1 Introduction
      2. A.3.2 Optical/visual inspection
      3. A.3.3 X-ray inspection
      4. A.3.4 Scanning acoustic microscopy
    4. Bibliography
  15. Appendix B: Destructive tools and tests
    1. B.1 Introduction
    2. B.2 Decapsulation
    3. B.3 Dye penetration
    4. B.4 Cross-sectioning and polishing
    5. B.5 Scanning electron microscopy (SEM)
    6. B.6 Transmission electron microscopy (TEM)
    7. B.7 Chemical and elemental tests
      1. B.7.1 Auger electron spectroscopy (AES)
      2. B.7.2 Energy-dispersive X-ray spectroscopy (EDS or EDX)
      3. B.7.3 Fourier transform infrared spectroscopy (FTIR)
      4. B.7.4 Secondary ion mass spectrometry (SIMS)
    8. B.8 Other analytical techniques
      1. B.8.1 Bonding wire pull
      2. B.8.2 Ball bond shear
      3. B.8.3 Differential scanning calorimetry (DSC)
      4. B.8.4 Flexural testing
    9. Bibliography
  16. Index

Product information

  • Title: Semiconductor Packaging
  • Author(s): Andrea Chen, Randy Hsiao-Yu Lo
  • Release date: April 2016
  • Publisher(s): CRC Press
  • ISBN: 9781439862070