
Interrupts
Address bus
Hold
Read/write
Effective
connection
under DMA
control
Figure 4.9 Basic scheme for a Direct Memory Access Controller
(DMAC)
boot-up program. The DMAC next sends a read or write
signal, as appropriate, via the peripheral driver to
memory so that data can then be transferred on the data
bus.
A useful facility of the DMAC, allowing it to handle
the transfer of blocks of data, is an automatic sequencing
mechanism controlled by a counter-register, that keeps
track of the number of bytes being transferred in a par-
ticular block. As an example of the possible speed of such
devices, the Motorola 6844 is capable of transferrin ...