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Vhdl for Logic Synthesis, Third Edition by Andrew Rushton

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Chapter 13

Test Benches

With most hardware description languages, the circuit description and the test waveforms are described in different ways, with the test waveforms described either using a waveform capture facility in the simulator or using a separate waveform language. Most VHDL simulators do not, however, have any form of waveform-capture facility because VHDL is itself sufficiently expressive to be used as a waveform language. The result is the test-bench, which is simply a naming convention for a VHDL model which generates waveforms with which to test a circuit model.

13.1 Test Benches

Test benches clearly only apply to the use of VHDL in simulation. They are not synthesised. Nevertheless, it is appropriate to have a chapter dedicated to the writing of test benches in a book on synthesis VHDL, since the writing of test benches is an important part of the design process and one where many designers get unnecessarily bogged down.

The necessity for test benches is clear. A synthesisable model should be extensively tested in simulation before synthesis to ensure correctness. A synthesiser works, as far as possible, on the principle that ‘what you simulate is what you get’ (WYSIWYG), so any errors in the design will be faithfully synthesised as errors in the final circuit. It is up to you as the designer to test carefully. Furthermore, this testing should be carried out on the RTL model prior to synthesis. This is where most errors can and should be found.

Diagnosing errors ...

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