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Vhdl for Logic Synthesis, Third Edition
book

Vhdl for Logic Synthesis, Third Edition

by Andrew Rushton
May 2011
Intermediate to advanced
484 pages
12h 50m
English
Wiley
Content preview from Vhdl for Logic Synthesis, Third Edition

List of Tables

Table 2.1 Scheduling and allocation for cross-product calculator

Table 2.2 Controller operations per clock cycle

Table 2.3 Comparison of synthesis results

Table 3.1 Event processing of adder tree

Table 3.2 Parity-generator functions

Table 4.1 Synthesisable types

Table 4.2 Standard types

Table 6.1 The synthesis type system

Table 6.2 Std_Logic_1164 types

Table 6.3 The meanings of the std_logic values

Table 6.4 Shift operators

Table 6.5 Shift and rotate operators for fixed_pkg

Table 6.6 Calculating result sizes for arithmetic operators

Table 6.7 Result sizes for arithmetic operators with identical input sizes

Table 6.8 Options controlling floating-point modes

Table 6.9 Results of classification function classfp

Table 6.10 Bit-preserving type conversions in fixed_pkg

Table 6.11 Bit-preserving type conversions in float_pkg

Table 6.12 Type conversion functions in numeric_std

Table 6.13 Type conversion functions in fixed_pkg

Table 6.14 Type conversion functions in float_pkg

Table 7.1 Type-conversion functions in std_logic_arith

Table 7.2 Permutations of types for all arithmetic operators

Table 7.3 Integer permutations for add, subtract

Table 7.4 Std_ulogic permutations for add, subtract

Table 10.1 Tap points for maximal-length PRBS generators

Table 11.1 Built-in operators for each type

Table 15.1 Filter coefficients for the low-pass filter

Table 15.2 Conversion of real coefficients to fixed-point

Table 15.3 Maximum error for different fixed-point sizes

Table 15.4 Maximum ...

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Publisher Resources

ISBN: 9780470688472Purchase book