August 2006

Intermediate to advanced

808 pages

21h 33m

English

Morgan Kaufmann

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In Praise of VLSI Test Principles and Architectures: Design for Testability
The Morgan Kaufmann Series in Systems on Silicon
Preface
In the Classroom
Acknowledgments
Contributors
About the Editors
1. Introduction
About this Chapter1.1. Importance of Testing1.2. Testing During the VLSI Lifecycle1.2.1. VLSI Development Process1.2.1.1. Design Verification1.2.1.2. Yield and Reject Rate1.2.2. Electronic System Manufacturing Process1.2.3. System-Level Operation1.3. Challenges in VLSI Testing1.3.1. Test Generation1.3.2. Fault Models1.3.2.1. Stuck-At Faults1.3.2.2. Transistor Faults1.3.2.3. Open and Short Faults1.3.2.4. Delay Faults and Crosstalk1.3.2.5. Pattern Sensitivity and Coupling Faults1.3.2.6. Analog Fault Models1.4. Levels of Abstraction in VLSI Testing1.4.1. Register-Transfer Level and Behavioral Level1.4.2. Gate Level1.4.3. Switch Level1.4.4. Physical Level1.5. Historical Review of VLSI Test Technology1.5.1. Automatic Test Equipment1.5.2. Automatic Test Pattern Generation1.5.3. Fault Simulation1.5.4. Digital Circuit Testing1.5.5. Analog and Mixed-Signal Circuit Testing1.5.6. Design for Testability1.5.7. Board Testing1.5.8. Boundary Scan Testing1.6. Concluding Remarks1.7. ExercisesAcknowledgmentsReferences
R1.0—BooksR1.1—Importance of TestingR1.3—Challenges in VLSI TestingR1.4—Levels of Abstraction in VLSI TestingR1.5—Historical Review of VLSI Test Technology

2. Design for Testability
About this Chapter2.1. Introduction2.2. Testability Analysis2.2.1. SCOAP Testability Analysis2.2.1.1. Combinational Controllability and Observability Calculation2.2.1.2. Sequential Controllability and Observability Calculation2.2.2. Probability-Based Testability Analysis2.2.3. Simulation-Based Testability Analysis2.2.4. RTL Testability Analysis2.3. Design for Testability Basics2.3.1. Ad Hoc Approach2.3.1.1. Test Point Insertion2.3.2. Structured Approach2.4. Scan Cell Designs2.4.1. Muxed-D Scan Cell2.4.2. Clocked-Scan Cell2.4.3. LSSD Scan Cell2.5. Scan Architectures2.5.1. Full-Scan Design2.5.1.1. Muxed-D Full-Scan Design2.5.1.2. Clocked Full-Scan Design2.5.1.3. LSSD Full-Scan Design2.5.2. Partial-Scan Design2.5.3. Random-Access Scan Design2.6. Scan Design Rules2.6.1. Tristate Buses2.6.2. Bidirectional I/O Ports2.6.3. Gated Clocks2.6.4. Derived Clocks2.6.5. Combinational Feedback Loops2.6.6. Asynchronous Set/Reset Signals2.7. Scan Design Flow2.7.1. Scan Design Rule Checking and Repair2.7.2. Scan Synthesis2.7.2.1. Scan Configuration2.7.2.2. Scan Replacement2.7.2.3. Scan Reordering2.7.2.4. Scan Stitching2.7.3. Scan Extraction2.7.4. Scan Verification2.7.4.1. Verifying the Scan Shift Operation2.7.4.2. Verifying the Scan Capture Operation2.7.5. Scan Design Costs2.8. Special-Purpose Scan Designs2.8.1. Enhanced Scan2.8.2. Snapshot Scan2.8.3. Error-Resilient Scan2.9. RTL Design for Testability2.9.1. RTL Scan Design Rule Checking and Repair2.9.2. RTL Scan Synthesis2.9.3. RTL Scan Extraction and Scan Verification2.10. Concluding Remarks2.11. ExercisesAcknowledgmentsReferences
R2.0—BooksR2.1—IntroductionR2.2—Testability AnalysisR2.3—Design for Testability BasicsR2.4—Scan Cell DesignsR2.5—Scan ArchitecturesR2.6—Scan Design RulesR2.7—Scan Design FlowR2.8—Special-Purpose Scan DesignsR2.9—RTL Design for TestabilityR2.10—Concluding Remarks
3. Logic and Fault Simulation
About this Chapter3.1. Introduction3.1.1. Logic Simulation for Design Verification3.1.2. Fault Simulation for Test and Diagnosis3.2. Simulation Models3.2.1. Gate-Level Network3.2.1.1. Sequential Circuits3.2.2. Logic Symbols3.2.2.1. Unknown State u3.2.2.2. High-Impedance State Z3.2.2.3. Intermediate Logic States3.2.3. Logic Element Evaluation3.2.3.1. Truth Tables3.2.3.2. Input Scanning3.2.3.3. Input Counting3.2.3.4. Parallel Gate Evaluation3.2.4. Timing Models3.2.4.1. Transport Delay3.2.4.2. Inertial Delay3.2.4.3. Wire Delay3.2.4.4. Functional Element Delay Model3.3. Logic Simulation3.3.1. Compiled-Code Simulation3.3.1.1. Logic Optimization3.3.1.2. Logic Levelization3.3.1.3. Code Generation3.3.2. Event-Driven Simulation3.3.2.1. Nominal-Delay Event-Driven Simulation3.3.3. Compiled-Code versus Event-Driven Simulation3.3.4. Hazards3.3.4.1. Static Hazard Detection3.3.4.2. Dynamic Hazard Detection3.4. Fault Simulation3.4.1. Serial Fault Simulation3.4.2. Parallel Fault Simulation3.4.2.1. Parallel Fault Simulation3.4.2.2. Parallel-Pattern Fault Simulation3.4.3. Deductive Fault Simulation3.4.4. Concurrent Fault Simulation3.4.5. Differential Fault Simulation3.4.6. Fault Detection3.4.7. Comparison of Fault Simulation Techniques3.4.8. Alternatives to Fault Simulation3.4.8.1. Toggle Coverage3.4.8.2. Fault Sampling3.4.8.3. Critical Path Tracing3.4.8.4. Statistical Fault Analysis3.5. Concluding Remarks3.6. ExercisesReferences
R3.0—BooksR3.1—IntroductionR3.2—Simulation ModelsR3.3—Logic SimulationR3.4—Fault SimulationR3.5—Concluding Remarks
4. Test Generation
About this Chapter4.1. Introduction4.2. Random Test Generation4.2.1. Exhaustive Testing4.3. Theoretical Background: Boolean Difference4.3.1. Untestable Faults4.4. Designing a Stuck-At ATPG for Combinational Circuits4.4.1. A Naive ATPG Algorithm4.4.1.1. Backtracking4.4.2. A Basic ATPG Algorithm4.4.3. D Algorithm4.4.4. PODEM4.4.5. FAN4.4.6. Static Logic Implications4.4.7. Dynamic Logic Implications4.5. Designing a Sequential ATPG4.5.1. Time Frame Expansion4.5.2. 5-Valued Algebra Is Insufficient4.5.3. Gated Clocks and Multiple Clocks4.6. Untestable Fault Identification4.6.1. Multiple-Line Conflict Analysis4.7. Designing a Simulation-Based ATPG4.7.1. Overview4.7.2. Genetic-Algorithm-Based ATPG4.7.2.1. Issues Concerning the GA Population4.7.2.2. Issues Concerning GA Parameters4.7.2.3. Issues Concerning the Fitness Function4.7.2.4. CASE Studies4.8. Advanced Simulation-Based ATPG4.8.1. Seeding the GA with Helpful Sequences4.8.2. Logic-Simulation-Based ATPG4.8.3. Spectrum-Based ATPG4.9. Hybrid Deterministic and Simulation-Based ATPG4.9.1. ALT-TEST Hybrid4.10. ATPG for Non-Stuck-At Faults4.10.1. Designing an ATPG That Captures Delay Defects4.10.1.1. Classification of Path-Delay Faults4.10.1.2. ATPG for Path-Delay Faults4.10.2. ATPG for Transition Faults4.10.3. Transition ATPG Using Stuck-At ATPG4.10.4. Transition ATPG Using Stuck-At Vectors4.10.4.1. Transition Test Chains via Weighted Transition Graph4.10.5. Bridging Fault ATPG4.11. Other Topics in Test Generation4.11.1. Test Set Compaction4.11.2. N-Detect ATPG4.11.3. ATPG for Acyclic Sequential Circuits4.11.4. IDDQ Testing4.11.5. Designing a High-Level ATPG4.12. Concluding Remarks4.13. ExercisesReferences
R4.1—IntroductionR4.2—Random Test GenerationR4.4—Designing a Stuck-At ATPG for Combinational CircuitsR4.5—Designing a Sequential ATPGR4.6—Untestable Fault IdentificationR4.7—Designing a Simulation-Based ATPGR4.8—Advanced Simulation-Based ATPGR4.9—Hybrid Deterministic and Simulation-Based ATPGR4.10—ATPG for Non-Stuck-At FaultsR4.11—Other Topics in Test Generation
5. Logic Built-In Self-Test
About this Chapter5.1. Introduction5.2. BIST Design Rules5.2.1. Unknown Source Blocking5.2.1.1. Analog Blocks5.2.1.2. Memories and Non-Scan Storage Elements5.2.1.3. Combinational Feedback Loops5.2.1.4. Asynchronous Set/Reset Signals5.2.1.5. Tristate Buses5.2.1.6. False Paths5.2.1.7. Critical Paths5.2.1.8. Multiple-Cycle Paths5.2.1.9. Floating Ports5.2.1.10. Bidirectional I/O Ports5.2.2. Re-Timing5.3. Test Pattern Generation5.3.1. Exhaustive Testing5.3.1.1. Binary Counter5.3.1.2. Complete LFSR5.3.2. Pseudo-Random Testing5.3.2.1. Maximum-Length LFSR5.3.2.2. Weighted LFSR5.3.2.3. Cellular Automata5.3.3. Pseudo-Exhaustive Testing5.3.3.1. Verification TestingSyndrome Driver CounterConstant-Weight CounterCombined LFSR/SRCombined LFSR/PSCondensed LFSRCyclic LFSRCompatible LFSR5.3.3.2. Segmentation Testing5.3.4. Delay Fault Testing5.3.5. Summary5.4. Output Response Analysis5.4.1. Ones Count Testing5.4.2. Transition Count Testing5.4.3. Signature Analysis5.4.3.1. Serial Signature Analysis5.4.3.2. Parallel Signature Analysis5.5. Logic BIST Architectures5.5.1. BIST Architectures for Circuits without Scan Chains5.5.1.1. A Centralized and Separate Board-Level BIST Architecture5.5.1.2. Built-In Evaluation and Self-Test (BEST)5.5.2. BIST Architectures for Circuits with Scan Chains5.5.2.1. LSSD On-Chip Self-Test5.5.2.2. Self-Testing Using MISR and Parallel SRSG5.5.3. BIST Architectures Using Register Reconfiguration5.5.3.1. Built-In Logic Block Observer5.5.3.2. Modified Built-In Logic Block Observer5.5.3.3. Concurrent Built-In Logic Block Observer5.5.3.4. Circular Self-Test Path (CSTP)5.5.4. BIST Architectures Using Concurrent Checking Circuits5.5.4.1. Concurrent Self-Verification5.5.5. Summary5.6. Fault Coverage Enhancement5.6.1. Test Point Insertion5.6.1.1. Test Point Placement5.6.1.2. Control Point Activation5.6.2. Mixed-Mode BIST5.6.2.1. ROM Compression5.6.2.2. LFSR Reseeding5.6.2.3. Embedding Deterministic Patterns5.6.3. Hybrid BIST5.7. BIST Timing Control5.7.1. Single-Capture5.7.1.1. One-Hot Single-Capture5.7.1.2. Staggered Single-Capture5.7.2. Skewed-Load5.7.2.1. One-Hot Skewed-Load5.7.2.2. Aligned Skewed-Load5.7.2.3. Staggered Skewed-Load5.7.3. Double-Capture5.7.3.1. One-Hot Double-Capture5.7.3.2. Aligned Double-Capture5.7.3.3. Staggered Double-Capture5.7.4. Fault Detection5.8. A Design Practice5.8.1. BIST Rule Checking and Violation Repair5.8.2. Logic BIST System Design5.8.2.1. Logic BIST Architecture5.8.2.2. TPG and ORA5.8.2.3. Test Controller5.8.2.4. Clock Gating Block5.8.2.5. Re-Timing Logic5.8.2.6. Fault Coverage Enhancing Logic and Diagnostic Logic5.8.3. RTL BIST Synthesis5.8.4. Design Verification and Fault Coverage Enhancement5.9. Concluding Remarks5.10. ExercisesAcknowledgmentsReferences
R5.0—BooksR5.2—BIST Design RulesR5.3—Test Pattern GenerationR5.4—Output Response AnalysisR5.5—Logic BIST ArchitecturesR5.6—Fault Coverage EnhancementR5.7—BIST Timing ControlR5.8—A Design PracticeR5.9—Concluding Remarks
6. Test Compression
About this Chapter6.1. Introduction6.2. Test Stimulus Compression6.2.1. Code-Based Schemes6.2.1.1. Dictionary Code (Fixed-to-Fixed)6.2.1.2. Huffman Code (Fixed-to-Variable)6.2.1.3. Run-Length Code (Variable-to-Fixed)6.2.1.4. Golomb Code (Variable-to-Variable)6.2.2. Linear-Decompression-Based Schemes6.2.2.1. Combinational Linear Decompressors6.2.2.2. Fixed-Length Sequential Linear Decompressors6.2.2.3. Variable-Length Sequential Linear Decompressors6.2.2.4. Combined Linear and Nonlinear Decompressors6.2.3. Broadcast-Scan-Based Schemes6.2.3.1. Broadcast Scan6.2.3.2. Illinois Scan6.2.3.3. Multiple-Input Broadcast Scan6.2.3.4. Reconfigurable Broadcast Scan6.2.3.5. Virtual Scan6.3. Test Response Compaction6.3.1. Space Compaction6.3.1.1. Zero-Aliasing Linear Compaction6.3.1.2. X-Compact6.3.1.3. X-Blocking6.3.1.4. X-Masking6.3.1.5. X-Impact6.3.2. Time Compaction6.3.3. Mixed Time and Space Compaction6.4. Industry Practices (Edited by Laung-Terng Wang)6.4.1. OPMISR+6.4.2. Embedded Deterministic Test6.4.3. VirtualScan and UltraScan6.4.4. Adaptive Scan6.4.5. ETCompression6.4.6. Summary6.5. Concluding Remarks6.6. ExercisesAcknowledgmentsReferences
R6.0—BooksR6.1—IntroductionR6.2—Test Stimulus CompressionR6.3—Test Response CompactionR6.4—Industry Practices
7. Logic Diagnosis
About this Chapter7.1. Introduction7.2. Combinational Logic Diagnosis7.2.1. Cause–Effect Analysis7.2.1.1. Compaction and Compression of Fault Dictionary7.2.2. Effect–Cause Analysis7.2.2.1. Structural Pruning7.2.2.2. Backtrace Algorithm7.2.2.3. Inject-and-Evaluate Paradigm7.2.3. Chip-Level Strategy7.2.3.1. Direct Partitioning7.2.3.2. Two-Phase Strategy7.2.3.3. Overall Chip-Level Diagnostic Flow7.2.4. Diagnostic Test Pattern Generation7.2.5. Summary of Combinational Logic Diagnosis7.3. Scan Chain Diagnosis7.3.1. Preliminaries for Scan Chain Diagnosis7.3.2. Hardware-Assisted Method7.3.3. Modified Inject-and-Evaluate Paradigm7.3.4. Signal-Profiling-Based Method7.3.4.1. Diagnostic Test Sequence Selection7.3.4.2. Run-and-Scan Test Application7.3.4.3. Why Functional Sequences?7.3.4.4. Profiling-Based Analysis7.3.5. Summary of Scan Chain Diagnosis7.4. Logic BIST Diagnosis7.4.1. Overview of Logic BIST Diagnosis7.4.2. Interval-Based Methods7.4.3. Masking-Based Methods7.5. Concluding Remarks7.6. ExercisesAcknowledgmentsReferences
R7.0—BooksR7.1—IntroductionR7.2—Combinational Logic DiagnosisR7.3—Scan Chain DiagnosisR7.4—Logic BIST Diagnosis
8. Memory Testing and Built-In Self-Test
About this Chapter8.1. Introduction8.2. RAM Functional Fault Models and Test Algorithms8.2.1. RAM Functional Fault Models8.2.2. RAM Dynamic Faults8.2.3. Functional Test Patterns and Algorithms8.2.4. March Tests8.2.5. Comparison of RAM Test Patterns8.2.6. Word-Oriented Memory8.2.7. Multi-Port Memory8.3. RAM Fault Simulation and Test Algorithm Generation8.3.1. Fault Simulation8.3.2. RAMSES8.3.3. Test Algorithm Generation by Simulation8.4. Memory Built-In Self-Test8.4.1. RAM Specification and BIST Design Strategy8.4.2. BIST Architectures and Functions8.4.3. BIST Implementation8.4.4. BRAINS: A RAM BIST Compiler8.5. Concluding Remarks8.6. ExercisesAcknowledgmentsReferences
R8.1—IntroductionR8.2—RAM Functional Fault Models and Test AlgorithmsR8.3—RAM Fault Simulation and Test Algorithm GenerationR8.4—Memory Built-In Self-Test
9. Memory Diagnosis and Built-In Self-Repair
About this Chapter9.1. Introduction9.1.1. Why Memory Diagnosis?9.1.2. Why Memory Repair?9.2. Refined Fault Models and Diagnostic Test Algorithms9.3. BIST with Diagnostic Support9.3.1. Controller9.3.2. Test Pattern Generator9.3.3. Fault Site Indicator (FSI)9.4. RAM Defect Diagnosis and Failure Analysis9.5. RAM Redundancy Analysis Algorithms9.5.1. Conventional Redundancy Analysis Algorithms9.5.2. The Essential Spare Pivoting Algorithm9.5.3. Repair Rate and Overhead9.6. Built-In Self-Repair9.6.1. Redundancy Organization9.6.2. BISR Architecture and Procedure9.6.3. BIST Module9.6.4. BIRA Module9.6.5. An Industrial Case9.6.6. Repair Rate and Yield9.7. Concluding Remarks9.8. ExercisesAcknowledgmentsReferences
R9.1—IntroductionR9.2—Refined Fault Models and Diagnostic Test AlgorithmsR9.3—BIST with Diagnostic SupportR9.4—RAM Defect Diagnosis and Failure AnalysisR9.5—RAM Redundancy Analysis AlgorithmsR9.6—Built-In Self-Repair
10. Boundary Scan and Core-Based Testing
About this Chapter10.1. Introduction10.1.1. IEEE 1149 Standard Family10.1.2. Core-Based Design and Test Considerations10.2. Digital Boundary Scan (IEEE Std. 1149.1)10.2.1. Basic Concept10.2.2. Overall 1149.1 Test Architecture and Operations10.2.3. Test Access Port and Bus Protocols10.2.4. Data Registers and Boundary-Scan Cells10.2.5. TAP Controller10.2.6. Instruction Register and Instruction Set10.2.7. Boundary-Scan Description Language10.2.8. On-Chip Test Support with Boundary Scan10.2.9. Board and System-Level Boundary-Scan Control Architectures10.3. Boundary Scan for Advanced Networks (IEEE 1149.6)10.3.1. Rationale for 1149.610.3.2. 1149.6 Analog Test Receiver10.3.3. 1149.6 Digital Driver Logic10.3.4. 1149.6 Digital Receiver Logic10.3.5. 1149.6 Test Access Port (TAP)10.3.6. Summary10.4. Embedded Core Test Standard (IEEE Std. 1500)10.4.1. SOC (System-on-Chip) Test Problems10.4.2. Overall Architecture10.4.3. Wrapper Components and Functions10.4.4. Instruction Set10.4.5. Core Test Language (CTL)10.4.6. Core Test Supporting and System Test Configurations10.4.7. Hierarchical Test Control and Plug-and-Play10.5. Comparisons between the 1500 and 1149.1 Standards10.6. Concluding Remarks10.7. ExercisesAcknowledgmentsReferences
R10.0—BooksR10.1—IntroductionR10.2—Digital Boundary Scan (IEEE Std. 1149.1)R10.3—Boundary-Scan Extension (IEEE Std. 1149.6)R10.4—Embedded Core Test Standard (IEEE Std. 1500)R10.6—Concluding Remarks
11. Analog and Mixed-Signal Testing
About this Chapter11.1. Introduction11.1.1. Analog Circuit Properties11.1.1.1. Continuous Signals11.1.1.2. Large Range of Circuits11.1.1.3. Nonlinear Characteristics11.1.1.4. Feedback Ambiguity11.1.1.5. Complicated Cause–Effect Relationship11.1.1.6. Absence of Suitable Fault Model11.1.1.7. Requirement for Accurate Instruments for Measuring Analog Signals11.1.2. Analog Defect Mechanisms and Fault Models11.1.2.1. Hard Faults11.1.2.2. Soft Faults11.2. Analog Circuit Testing11.2.1. Analog Test Approaches11.2.2. Analog Test Waveforms11.2.3. DC Parametric Testing11.2.3.1. Open-Loop Gain Measurement11.2.3.2. Unit Gain Bandwidth Measurement11.2.3.3. Common Mode Rejection Ratio Measurement11.2.3.4. Power Supply Rejection Ratio Measurement11.2.4. AC Parametric Testing11.2.4.1. Maximal Output Amplitude Measurement11.2.4.2. Frequency Response Measurement11.2.4.3. SNR and Distortion Measurement11.2.4.4. Intermodulation Distortion Measurement11.3. Mixed-Signal Testing11.3.1. Introduction to Analog–Digital Conversion11.3.2. ADC and DAC Circuit Structure11.3.2.1. DAC Circuit Structure11.3.2.2. ADC Circuit Structure11.3.3. ADC/DAC Specification and Fault Models11.3.4. IEEE 1057 Standard11.3.5. Time-Domain ADC Testing11.3.5.1. Code Bins11.3.5.2. Code Transition Level Test (Static)11.3.5.3. Code Transition Level Test (Dynamic)11.3.5.4. Gain and Offset Test11.3.5.5. Linearity Error and Maximal Static Error11.3.5.6. Sine Wave Curve-Fit Test11.3.6. Frequency-Domain ADC Testing11.4. IEEE 1149.4 Standard for a Mixed-Signal Test Bus11.4.1. IEEE 1149.4 Overview11.4.1.1. Scope of the Standard11.4.2. IEEE 1149.4 Circuit Structures11.4.3. IEEE 1149.4 Instructions11.4.3.1. Mandatory Instructions11.4.3.2. Optional Instructions11.4.4. IEEE 1149.4 Test Modes11.4.4.1. Open/Short Interconnect Testing11.4.4.2. Extended Interconnect Measurement11.4.4.3. Complex Network Measurement11.4.4.4. High-Performance Configuration11.5. Concluding Remarks11.6. ExercisesAcknowledgmentsReferences
R11.0—BooksR11.1—IntroductionR11.2—Analog Circuit Testing
12. Test Technology Trends in the Nanometer Age
About this Chapter12.1. Test Technology Roadmap12.2. Delay Testing12.2.1. Test Application Schemes for Testing Delay Defects12.2.2. Delay Fault Models12.2.3. Summary12.3. Coping with Physical Failures, Soft Errors, and Reliability Issues12.3.1. Signal Integrity and Power Supply Noise12.3.1.1. Integrity Loss Fault Model12.3.1.2. Location12.3.1.3. Pattern Generation12.3.1.4. Sensing and Readout12.3.2. Parametric Defects, Process Variations, and Yield12.3.2.1. Defect-Based Test12.3.3. Soft Errors12.3.4. Fault Tolerance12.3.5. Defect and Error Tolerance12.4. FPGA Testing12.4.1. Impact of Programmability12.4.2. Testing Approaches12.4.3. Built-In Self-Test of Logic Resources12.4.4. Built-In Self-Test of Routing Resources12.4.5. Recent Trends12.5. MEMS Testing12.5.1. Basic Concepts for Capacitive MEMS Devices12.5.2. MEMS Built-In Self-Test12.5.2.1. Sensitivity BIST Scheme12.5.2.2. Symmetry BIST Scheme12.5.2.3. A Dual-Mode BIST Technique12.5.3. A BIST Example for MEMS Comb Accelerometers12.5.4. Conclusions12.6. High-speed I/O Testing12.6.1. I/O Interface Technology and Trend12.6.2. I/O Testing and Challenges12.6.3. High-Performance I/O Test Solutions12.6.4. Future Challenges12.7. RF Testing12.7.1. Core RF Building Blocks12.7.2. RF Test Specifications and Measurement Procedures12.7.2.1. Gain12.7.2.2. Conversion Gain12.7.2.3. Third-Order Intercept12.7.2.4. Noise Figure12.7.3. Tests for System-Level Specifications12.7.3.1. Adjacent Channel Power Ratio12.7.3.2. Error Vector Magnitude, Magnitude Error, and Phase Error12.7.4. Current and Future Trends12.7.4.1. Future Trends12.8. Concluding RemarksAcknowledgmentsReferences
R12.0—BooksR12.1—Test Technology RoadmapR12.2—Delay TestingR12.3—Coping with Physical Failures, Soft Errors, and Reliability IssuesR12.4—FPGA TestingR12.5—MEMS TestingR12.6—High-Speed I/O TestingR12.7—RF TestingR12.8—Concluding Remarks

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