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Embedded Systems Architecture by Daniele Lacamera

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Multi-master

I2C offers a deterministic mechanism to detect and react to the presence of multiple masters on the bus, which is again based on the electrical property of the SDA line.

Before initiating any communication, the master ensures that the bus is available by sensing the SDA and SCL lines. The way the START condition is designed can already rule out most of the conflicts. Concurrent start conditions can be interrupted whenever the SDA line is sensed low in the initial grace time in between the two edges. This mechanism alone does not prevent two I2C masters to access the channel at the same time, because conflicts are still possible due to the propagation time of the signal across the wire.

Two master devices that initiate a transaction ...

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