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Embedded Systems Architecture by Daniele Lacamera

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Interrupt-based SPI transfers

The interface to enable the interrupt for the SPI transceiver is in fact very similar to that of UART seen in the previous section. In order for non-blocking transactions to be correctly implemented, they have to be split between their read and write phases to allow events to trigger the associated actions.

Setting these two bits in the SPI1_CR2 register will enable the interrupt trigger upon an empty transmit FIFO and a non-empty receive FIFO, respectively:

#define SPI_CR2_TXEIE (1 << 7)#define SPI_CR2_RXNEIE (1 << 6)

The associated service routine, included in the interrupt vector, can still peek from the values in SPI1_SR to advance the transaction to the next phase:

void isr_spi1(void){ volatile uint32_t ...

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