From ASICs to SOCs: A Practical Approach

PLL Basics

A simplified block diagram of a PLL is shown in Figure C.1. The reference clock, REFclk, is the input clock into the ASIC. The PLL tracks the reference clock and adjusts the phase of its output, PLLout, such that REFclk and the feedback clock, FBclk, are in phase.

Figure C.1. Phase-Locked Loop Block Diagram

The phase detector compares the phase difference between the rising edge of REFclk and the rising edge of FBclk. When the two are not aligned, the phase-detector output changes to increase or decrease the voltage level on the output on the charge pump.

The charge pump and low-pass filter convert the digital output of the phase detector ...