From ASICs to SOCs: A Practical Approach

PLL Errors

PLLs don't exhibit ideal behavior. A PLL will not perfectly align t_FB and t_REF, and the delays through an ASIC clock-distribution network are never perfectly balanced. For purposes of timing analysis, the PLL errors to consider are as follows.

Static-Phase Error (SPE)

SPE is the fixed offset (error) between the rising edges of REFclk and FBclk caused by delay-path differences in the phase detector, process/voltage/temperature differences with the ASIC, and transition-time (slew-rate) differences on the REFclk and FBclk inputs to the PLL.

Long-Term Jitter (LTJ)

LTJ is a low-frequency drift in the offset between the rising edges of REFclk and FBclk.

Short-Term Jitter (STJ)

STJ is a high-frequency drift in the offset between the rising ...