May 2003
Intermediate to advanced
192 pages
3h 50m
English
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5.6. Summary
In this chapter, sources of power dissipation in CMOS devices were discussed.
The fundamental power equation
is the basis for all power reduction techniques. Each term in the equation can contribute to power savings.
Several methods of power optimization at different levels of design abstraction for ASICs and SOCs were explained. These techniques are:
Algorithm-level optimization
Architecture-level optimization
RT-level optimization
Gate-level optimization
In addition to power-optimization techniques, the simulation-based power-estimation method was discussed. Low-power EDA tools for predicting power at different levels of design abstraction ...
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I’ve been on the O’Reilly platform for more than eight years. I use a couple of learning platforms, but I'm on O'Reilly more than anybody else. When you're there, you start learning. I'm never disappointed.Amir M.
I'm always learning. So when I got on to O'Reilly, I was like a kid in a candy store. There are playlists. There are answers. There's on-demand training. It's worth its weight in gold, in terms of what it allows me to do.