From ASICs to SOCs: A Practical Approach

PLL Ideal Behavior

A PLL will adjust the phase of its output such that its reference input REFclk and its feedback clock are perfectly aligned, or in phase.

Consider the ASIC PLL circuit shown in Figure C.2. In this ideal circuit, the PLL will perfectly align the arrival time of the feedback clock, t_FB, with the arrival time of the reference clock, t_REF (t_FB = t_REF). The output of the PLL is distributed throughout the ASIC with the use of a clock-distribution network that is perfectly balanced such that the delay from the PLL output to every ASIC register is equal (dly_a = dly_b).

Figure C.2. Ideal PLL Behavior

The arrival time of the PLL output ...