From ASICs to SOCs: A Practical Approach

4.4. Modern Physical Design Techniques

In the age of deep submicron design, where 10+ million gates of logic have to fit on a single device running at 250+ MHz, traditional physical-design techniques are not capable of handling these new challenges. The problems with the traditional physical-design techniques can be summarized as follows:

• Timing closure is either unachievable or takes too long to finish.

• Too many iterations between front end and back end for each design.

• Unroutable designs for the target die size.

As the device geometries shrink to 0.11 micron and beyond, new tools, techniques, and methodologies are needed to overcome the problems we face with traditional approaches.

Here in this section, we cover two examples of modern physical-design ...