
48 High Performance Programming for Soft Computing
In Fig. 2.14a memory is one word wide, and all the access is achieved
sequentially. In Fig. 2.14b the bandwidth is increased by widening the
system memory and buses to connect memory to the processor with the aim
to allow parallel access to all the words in the block; a multiplexor is used
on reads as well as in control logic to update the appropriated words of the
cache on writes. The bandwidth is proportionally enlarged by increasing
the width of the memory and the bus, which decrease both the access time
and transfer time portions of the miss penalty. One option is to organize in
banks to ...