Decoupling the Front End from the Back EndThe Issue PhaseThe Completion PhaseThe P6's Issue Phase: The Reservation StationThe P6's Completion Phase: The Reorder BufferThe Instruction WindowThe P6 PipelineBranch Prediction on the P6The P6 Back EndCISC, RISC, and Instruction Set TranslationThe P6 Microarchitecture's Instruction Decoding UnitThe Cost of x86 Legacy Support on the P6Summary: The P6 Microarchitecture in Historical ContextThe Pentium ProThe Pentium IIThe Pentium III