An Overview of the G4e's Architecture and Pipeline

The diagram in Figure 7-4 shows the basics of the G4e’s microarchitecture, with an emphasis on representing the pipeline stages of the front end and back end. You might want to mark this page so you can refer to it throughout this section.

The basic microarchitecture of the G4e

Figure 7-4. The basic microarchitecture of the G4e

Before instructions can enter the G4e’s pipeline, they have to be available in its 32KB instruction cache. This instruction cache, together with the 32KB data cache, makes up the G4e’s 64KB L1 cache. An instruction leaves the L1 and goes down through the various front-end stages until it hits the back end, at which ...

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