Core's Back End

One of the most distinctive features of the older P6 design is its back end’s issue port structure, described in Chapter 5. Core uses a similar structure in its back end, although there are some major differences between the issue port and reservation station (RS) combination of Core and that of the P6.

To get a sense of the historical development of the issue port scheme, let’s take a look at the back end of the original Pentium Pro.

As you can see from Figure 12-12, ports 0 and 1 host the arithmetic hardware, while ports 2, 3, and 4 host the memory access hardware. The P6 core’s reservation station is capable of issuing up to five instructions per cycle to the execution units—one instruction per issue port per cycle.

As the P6 core ...

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