book

Inside the Machine

Name: Inside the Machine
Author: Jon Stokes
ISBN: 9781593271046

by Jon Stokes

December 2006

Beginner

320 pages

11h 17m

English

No Starch Press

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Inside the Machine
Preface
Acknowledgments
Introduction
1. Basic Computing Concepts
The Calculator Model of Computing
The File-Clerk Model of Computing
The Stored-Program ComputerRefining the File-Clerk Model
The Register File
RAM: When Registers Alone Won't Cut It
The File-Clerk Model Revisited and ExpandedAn Example: Adding Two Numbers
A Closer Look at the Code Stream: The Program
General Instruction TypesThe DLW-1's Basic Architecture and Arithmetic Instruction FormatThe DLW-1's Arithmetic Instruction FormatThe DLW-1's Memory Instruction FormatAn Example DLW-1 Program
A Closer Look at Memory Accesses: Register vs. Immediate
Immediate ValuesRegister-Relative Addressing

2. The Mechanics of Program Execution
Opcodes and Machine LanguageMachine Language on the DLW-1Binary Encoding of Arithmetic InstructionsBinary Encoding of Memory Access InstructionsThe load InstructionThe store InstructionTranslating an Example Program into Machine Language
The Programming Model and the ISA
The Programming ModelThe Instruction Register and Program CounterThe Instruction Fetch: Loading the Instruction RegisterRunning a Simple Program: The Fetch-Execute Loop
The Clock
Branch Instructions
Unconditional BranchConditional BranchBranch Instructions and the Fetch-Execute LoopThe Branch Instruction as a Special Type of LoadBranch Instructions and Labels
Excursus: Booting Up
3. Pipelined Execution
The Lifecycle of an Instruction
Basic Instruction Flow
Pipelining Explained
Applying the Analogy
A Non-Pipelined ProcessorA Pipelined ProcessorShrinking the ClockShrinking Program Execution TimeThe Speedup from PipeliningProgram Execution Time and Completion RateThe Relationship Between Completion Rate and Program Execution TimeInstruction Throughput and Pipeline StallsInstruction ThroughputPipeline StallsInstruction Latency and Pipeline StallsLimits to PipeliningClock Period and Completion RateThe Cost of Pipelining
4. Superscalar Execution
Superscalar Computing and IPC
Expanding Superscalar Processing with Execution Units
Basic Number Formats and Computer ArithmeticArithmetic Logic UnitsMemory-Access Units
Microarchitecture and the ISA
A Brief History of the ISAMoving Complexity from Hardware to Software
Challenges to Pipelining and Superscalar Design
Data HazardsStructural HazardsThe Register FileControl Hazards
5. The Intel Pentium and Pentium Pro
The Original PentiumCachesThe Pentium's PipelineThe Branch Unit and Branch PredictionThe Pentium's Back EndThe Integer ALUsThe Floating-Point ALUx86 Overhead on the PentiumSummary: The Pentium in Historical Context
The Intel P6 Microarchitecture: The Pentium Pro
Decoupling the Front End from the Back EndThe Issue PhaseThe Completion PhaseThe P6's Issue Phase: The Reservation StationThe P6's Completion Phase: The Reorder BufferThe Instruction WindowThe P6 PipelineBranch Prediction on the P6The P6 Back EndCISC, RISC, and Instruction Set TranslationThe P6 Microarchitecture's Instruction Decoding UnitThe Cost of x86 Legacy Support on the P6Summary: The P6 Microarchitecture in Historical ContextThe Pentium ProThe Pentium IIThe Pentium III
Conclusion
6. PowerPC Processors: 600 Series, 700 Series, and 7400
A Brief History of PowerPC
The PowerPC 601
The 601's Pipeline and Front EndThe PowerPC Instruction QueueInstruction Scheduling on the 601The 601's Back EndThe Integer UnitThe Floating-Point UnitThe Branch Execution UnitThe Sequencer UnitLatency and Throughput RevisitedSummary: The 601 in Historical Context
The PowerPC 603 and 603e
The 603e's Back EndThe 603e's Front End, Instruction Window, and Branch PredictionSummary: The 603 and 603e in Historical Context
The PowerPC 604
The 604's Pipeline and Back EndThe 604's Front End and Instruction WindowThe Issue Phase: The 604's Reservation StationsThe Four Rules of Instruction DispatchThe Completion Phase: The 604's Reorder BufferSummary: The 604 in Historical Context
The PowerPC 604e
The PowerPC 750 (aka the G3)
The 750's Front End, Instruction Window, and Branch InstructionSummary: The PowerPC 750 in Historical Context
The PowerPC 7400 (aka the G4)
The G4's Vector UnitSummary: The PowerPC G4 in Historical Context
Conclusion
7. Intel's Pentium 4 vs. Motorola's G4e: Approaches and Design Philosophies
The Pentium 4's Speed Addiction
The General Approaches and Design Philosophies of the Pentium 4 and G4e
An Overview of the G4e's Architecture and Pipeline
Stages 1 and 2: Instruction FetchStage 3: Decode/DispatchStage 4: IssueStage 5: ExecuteStages 6 and 7: Complete and Write-Back
Branch Prediction on the G4e and Pentium 4
An Overview of the Pentium 4's Architecture
Expanding the Instruction WindowThe Trace CacheShortening Instruction Execution TimeThe Trace Cache's Operation
An Overview of the Pentium 4's Pipeline
Stages 1 and 2: Trace Cache Next Instruction PointerStages 3 and 4: Trace Cache FetchStage 5: DriveStages 6 Through 8: Allocate and Rename (ROB)Stage 9: QueueStages 10 Through 12: ScheduleStages 13 and 14: IssueStages 15 and 16: Register FilesStage 17: ExecuteStage 18: FlagsStage 19: Branch CheckStage 20: DriveStages 21 and Onward: Complete and Commit
The Pentium 4's Instruction Window
8. Intel's Pentium 4 vs. Motorola's G4e: The Back End
Some Remarks About Operand Formats
The Integer Execution Units
The G4e's IUs: Making the Common Case FastThe Pentium 4's IUs: Make the Common Case Twice as Fast
The Floating-Point Units (FPUs)
The G4e's FPUThe Pentium 4's FPUConcluding Remarks on the G4e's and Pentium 4's FPUs
The Vector Execution Units
A Brief Overview of Vector ComputingVectors Revisited: The AltiVec Instruction SetAltiVec Vector OperationsIntra-Element Arithmetic and Non-Arithmetic InstructionsInter-Element Arithmetic and Non-Arithmetic InstructionsThe G4e's VU: SIMD Done RightIntel's MMXSSE and SSE2The Pentium 4's Vector Unit: Alphabet Soup Done QuicklyIncreasing Floating-Point Performance with SSE2
Conclusions
9. 64-Bit Computing and x86-64
Intel's IA-64 and AMD's x86-64
Why 64 Bits?
What Is 64-Bit Computing?
Current 64-Bit Applications
Dynamic RangeThe Benefits of Increased Dynamic Range, or, How the Existing 64-Bit Computing Market Uses 64-Bit IntegersVirtual Address Space vs. Physical Address SpaceThe Benefits of a 64-Bit Address
The 64-Bit Alternative: x86-64
Extended RegistersMore RegistersSwitching ModesOut with the Old
Conclusion
10. The G5: IBM's PowerPC 970
Overview: Design Philosophy
Caches and Front End
Branch Prediction
The Trade-Off: Decode, Cracking, and Group Formation
Dispatching and Issuing Instructions on the PowerPC 970The 970's Dispatch RulesPredecoding and Group DispatchSome Preliminary Conclusions on the 970's Group Dispatch Scheme
The PowerPC 970's Back End
Integer Unit, Condition Register Unit, and Branch UnitThe Integer Units Are Not Fully SymmetricInteger Unit Latencies and ThroughputThe CRUThe PowerPC Condition RegisterPreliminary Conclusions About the 970's Integer Performance
Load-Store Units
Front-Side Bus
The Floating-Point Units
Vector Computing on the PowerPC 970
Floating-Point Issue Queues
Integer and Load-Store Issue QueuesBU and CRU Issue QueuesVector Issue Queues
The Performance Implications of the 970's Group Dispatch Scheme
Conclusions
11. Understanding Caching and Performance
Caching BasicsThe Level 1 CacheThe Level 2 CacheExample: A Byte's Brief Journey Through the Memory HierarchyCache Misses
Locality of Reference
Spatial Locality of DataSpatial Locality of CodeTemporal Locality of Code and DataLocality: Conclusions
Cache Organization: Blocks and Block Frames
Tag RAM
Fully Associative Mapping
Direct Mapping
N-Way Set Associative Mapping
Four-Way Set Associative MappingTwo-Way Set Associative MappingTwo-Way vs. Direct-MappedTwo-Way vs. Four-WayAssociativity: Conclusions
Temporal and Spatial Locality Revisited: Replacement/Eviction Policies and Block Sizes
Types of Replacement/Eviction PoliciesBlock Sizes
Write Policies: Write-Through vs. Write-Back
Conclusions
12. Intel's Pentium M, Core Duo, and Core 2 Duo
Code Names and Brand Names
The Rise of Power-Efficient Computing
Power Density
Dynamic Power DensityStatic Power Density
The Pentium M
The Fetch PhaseThe Hardware Loop BufferThe Decode Phase: Micro-ops FusionFused StoresFused LoadsThe Impact of Micro-ops FusionBranch PredictionThe Loop DetectorThe Indirect PredictorThe Stack Execution UnitPipeline and Back EndSummary: The Pentium M in Historical Context
Core Duo/Solo
Intel's Line Goes Multi-CoreProcessor Organization and Core MicroarchitectureMultiprocessing and Chip MultiprocessingCore Duo's ImprovementsMicro-ops Fusion of SSE and SSE2 store and load-op InstructionsMicro-ops Fusion and Lamination of SSE and SSE2 Arithmetic InstructionsMicro-ops Fusion of Miscellaneous Non-SSE InstructionsImproved Loop DetectorSSE3Floating-Point ImprovementInteger Divide ImprovementVirtualization TechnologySummary: Core Duo in Historical Context
Core 2 Duo
The Fetch PhaseMacro-FusionThe Decode PhaseCore's Pipeline
Core's Back End
Integer UnitsFloating-Point UnitsVector Processing Improvements128-bit Vector Execution on the P6 Through Core Duo128-bit Vector Execution on CoreMemory Disambiguation: The Results Stream Version of Speculative ExecutionThe Lifecycle of a Memory Access InstructionThe Memory Reorder BufferMemory AliasingMemory Reordering RulesFalse AliasingMemory DisambiguationSummary: Core 2 Duo in Historical Context
A. Bibliography and Suggested Reading
Online Resources
Index
About the Author
Colophon
B. Updates

Content preview from Inside the Machine

The Trade-Off: Decode, Cracking, and Group Formation

As noted earlier, IBM’s PowerPC 970 fetches eight instructions per cycle from the L1 cache into an instruction queue, from which the instructions are pulled for decoding at a rate of eight per cycle. This compares quite favorably to the G4e’s four instructions per cycle fetch and decode rate.

Much like the Pentium 4 and its predecessor, the P6, the PowerPC 970 translates PowerPC instructions into an 86-bit internal instruction format that not only makes the instructions easier for the back end to schedule, but also explicitly encodes register dependency information. IBM calls these internal instructions IOPs, presumably short for internal operations. Like micro-ops on the Pentium 4, it is these ...

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Inside the Machine

by Jon Stokes

The Trade-Off: Decode, Cracking, and Group Formation

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