RapidIO: The Next Generation Communication Fabric For Embedded Application

Table of contents

1. Copyright
2. PREFACE
3. The Interconnect Problem
   1. PROCESSOR PERFORMANCE AND BANDWIDTH GROWTH
   2. MULTIPROCESSING
   3. SYSTEM OF SYSTEMS
   4. PROBLEMS WITH TRADITIONAL BUSES
   5. THE MARKET PROBLEM
   6. RAPIDIO: A NEW APPROACH
   7. WHERE WILL IT BE USED?
   8. AN ANALOGY
4. RapidIO Technology
   1. PHILOSOPHY
   2. THE SPECIFICATION HIERARCHY
   3. RAPIDIO PROTOCOL OVERVIEW
   4. PACKET FORMAT
   5. TRANSACTION FORMATS AND TYPES
   6. MESSAGE PASSING
   7. GLOBALLY SHARED MEMORY
   8. FUTURE EXTENSIONS
   9. FLOW CONTROL
   10. THE PARALLEL PHYSICAL LAYER
   11. THE SERIAL PHYSICAL LAYER
   12. LINK PROTOCOL
   13. MAINTENANCE AND ERROR MANAGEMENT
   14. PERFORMANCE
   15. OPERATION LATENCY
5. Devices, Switches, Transactions and Operations
   1. PROCESSING ELEMENT MODELS
   2. I/O PROCESSING ELEMENT
   3. SWITCH PROCESSING ELEMENT
   4. OPERATIONS AND TRANSACTIONS
6. I/O Logical Operations
   1. INTRODUCTION
   2. REQUEST CLASS TRANSACTIONS
   3. RESPONSE CLASS TRANSACTIONS
   4. A SAMPLE READ OPERATION
   5. WRITE OPERATIONS
   6. STREAMING WRITES
   7. ATOMIC OPERATIONS
   8. MAINTENANCE OPERATIONS
   9. DATA ALIGNMENT
7. Messaging Operations
   1. INTRODUCTION
   2. MESSAGE TRANSACTIONS
   3. MAILBOX STRUCTURES
   4. OUTBOUND MAILBOX STRUCTURES
8. System Level Addressing in RapidIO Systems
   1. SYSTEM TOPOLOGY
   2. SWITCH-BASED SYSTEMS
   3. SYSTEM PACKET ROUTING
   4. FIELD ALIGNMENT AND DEFINITION
   5. ROUTING MAINTENANCE PACKETS
9. The Serial Physical Layer
   1. PACKETS
   2. CONTROL SYMBOLS
   3. PCS AND PMA LAYERS
   4. USING THE SERIAL PHYSICAL LAYER
   5. TRANSACTION AND PACKET DELIVERY ORDERING RULES
   6. ERROR DETECTION AND RECOVERY
   7. RETIMERS AND REPEATERS
   8. THE ELECTRICAL INTERFACE
10. Parallel Physical Layer Protocol
    1. PACKET FORMATS
    2. CONTROL SYMBOL FORMATS
    3. PACKET START AND CONTROL SYMBOL DELINEATION
    4. PACKET EXCHANGE PROTOCOL
    5. FIELD PLACEMENT AND DEFINITION
    6. LINK MAINTENANCE PROTOCOL
    7. PACKET TERMINATION
    8. PACKET PACING
    9. EMBEDDED CONTROL SYMBOLS
    10. PACKET ALIGNMENT
    11. SYSTEM MAINTENANCE
    12. SYSTEM CLOCKING CONSIDERATIONS
    13. BOARD ROUTING GUIDELINES
11. Interoperating with PCI Technologies
    1. ADDRESS MAP CONSIDERATIONS
    2. TRANSACTION FLOW
    3. PCI-X TO RAPIDIO TRANSACTION FLOW
    4. RAPIDIO TO PCI TRANSACTION MAPPING
    5. OPERATION ORDERING AND TRANSACTION DELIVERY
    6. INTERACTIONS WITH GLOBALLY SHARED MEMORY
    7. BYTE LANE AND BYTE ENABLE USAGE
    8. ERROR MANAGEMENT
12. RapidIO Bringup and Initialization Programming
    1. OVERVIEW OF THE SYSTEM BRINGUP PROCESS
    2. SYSTEM APPLICATION PROGRAMMING INTERFACES
    3. SYSTEM BRINGUP EXAMPLE
13. Advanced Features
    1. SYSTEM-LEVEL FLOW CONTROL
    2. ERROR MANAGEMENT EXTENSIONS
    3. MEMORY COHERENCY SUPPORT
    4. MULTICASTING TRANSACTIONS IN RAPIDIO
    5. MULTICASTING SYMBOLS
14. Data Streaming Logical Layer
    1. INTRODUCTION
    2. TYPE 9 PACKET FORMAT (DATA STREAMING CLASS)
    3. VIRTUAL STREAMS
    4. CONFIGURING DATA STREAMING SYSTEMS
    5. ADVANCED TRAFFIC MANAGEMENT
    6. USING DATA STREAMING
15. Applications of the RapidIO Interconnect Technology
    1. RAPIDIO IN STORAGE SYSTEMS
    2. RAPIDIO IN CELLULAR WIRELESS INFRASTRUCTURE
    3. FAULT-TOLERANT SYSTEMS AND RAPIDIO
16. Developing RapidIO Hardware
    1. INTRODUCTION
    2. IMPLEMENTING A RAPIDIO END POINT
    3. SUPPORTING FUNCTIONS
    4. IMPLEMENTING A RAPIDIO SWITCH
    5. SUMMARY
17. Implementation Benefits of the RapidIO Interconnect Technology in FPGAs
    1. BUILDING THE ECOSYSTEM
    2. ADVANCES IN FPGA TECHNOLOGY
    3. MULTI PROTOCOL SUPPORT FOR THE EMBEDDED ENVIRONMENT
    4. SIMPLE HANDSHAKE
    5. LOW BUFFERING OVERHEAD
    6. EFFICIENT ERROR COVERAGE
    7. CONCLUSION
18. Application of RapidIO to Mechanical Environments
    1. HELPFUL FEATURES FOR MECHANICAL ENVIRONMENTS
    2. CHANNEL CHARACTERISTICS
    3. INDUSTRY STANDARD MECHANICAL PLATFORMS SUPPORTING RAPIDIO
    4. SUMMARY
19. RapidIO Logical and Transport Layer Registers
    1. RESERVED REGISTER AND BIT BEHAVIOR
    2. CAPABILITY REGISTERS (CARs)
    3. COMMAND AND STATUS REGISTERS (CSRs)
    4. EXTENDED FEATURES DATA STRUCTURE
20. Serial Physical Layer Registers
    1. GENERIC END POINT DEVICES
    2. Register Maps
    3. GENERIC END POINT DEVICES: SOFTWARE-ASSISTED ERROR RECOVERY OPTION
21. Parallel Physical Layer Registers
    1. GENERIC END POINT DEVICES
    2. GENERIC END POINT DEVICES: SOFTWARE-ASSISTED ERROR RECOVERY OPTION
    3. SWITCH DEVICES
22. Error Management Extensions Registers
    1. ADDITIONS TO EXISTING REGISTERS
    2. NEW ERROR MANAGEMENT REGISTER