Itanium® Architecture for Programmers: Understanding 64-Bit Processors and EPIC Principles

D.2. General Registers and NaT Bits

The Itanium architecture defines 128 general-purpose registers (Gr₀–Gr₁₂₇), which are 64 bits in width and can thus accommodate address pointers and either signed or unsigned integers of that size:

Associated with each general register is a 65th bit, called the NaT bit (not a thing). When a NaT bit is set, the CPU knows that the contents of the associated general register cannot be relied upon.

When data from a marked register are used in subsequent calculations, or if a copy is made of the register's contents, the NaT bit will automatically be set for whichever destination register holds the new invalid result. ...